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spi.h

   1  /*******************************************************************************
   2     spi.h:
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42     Popis:
  43       Sdileny ovladac pro flash pamet and FPGA SpartanIII.
  44  *******************************************************************************/
  45  
  46  
  47  #ifndef _SPI_H_
  48  #define _SPI_H_
  49  
  50  // SPI rozhrani pro komunikaci s FPGA a externi FLASH
  51  
  52  
  53  
  54  
  55  #define DONE        BIT7        ///< DONE vstup do FPGA
  56  
  57  
  58  
  59  #define SPI_PORT_DIR   P5DIR       ///< direct port
  60  
  61  
  62  
  63  
  64  #if defined MSP_16X
  65   #define SPI_RX_BUF U1RXBUF
  66   #define SPI_TX_BUF U1TXBUF
  67  // #define SPI_TX_BUF_FULL ((TXEPT & U1TCTL) == 0)
  68   #define SPI_BUSY ((TXEPT & U1TCTL) == 0)
  69  #elif defined MSP_261X
  70   #define SPI_RX_BUF UCB1RXBUF
  71   #define SPI_TX_BUF UCB1TXBUF
  72  // #define SPI_TX_BUF_FULL ((UC1IFG & UCB1TXIFG) == 0)
  73   #define SPI_BUSY ((UCBUSY & UCB1STAT) != 0)
  74  // #define SPI_BUSY (!(UC1IFG & UCB1TXIFG))
  75  #else
  76   #error "SPI define"
  77  #endif
  78  
  79  /**
  80   \brief Inicializace SPI
  81   **/
  82  void SPI_Init(void);
  83  
  84  /**
  85   \brief Deaktivace SPI
  86   **/
  87  void SPI_Close(void);
  88  
  89  inline unsigned char SPI_read_wait_write(unsigned char datain);
  90  
  91  inline unsigned char SPI_write_wait_read(unsigned char datain);
  92  
  93  /**
  94  
  95  
  96  
  97   **/
  98  #define SPI_read_write SPI_write_wait_read
  99  
 100  
 101  /**
 102  
 103   \param active - 1 - aktivni CS
 104                    \n jinak neaktivni
 105   **/
 106  #define SPI_set_cs_FLASH(active) \
 107    {  SPI_PORT_OUT = ((active) == 0) ? (SPI_PORT_OUT | SPI_CSn) : (SPI_PORT_OUT & ~SPI_CSn); }
 108  
 109  
 110  /**
 111  
 112   \param active - 1 - aktivni CS
 113                    \n jinak neaktivni
 114   **/
 115  #define SPI_set_cs_FPGA(active) \
 116     { SPI_PORT_OUT = ((active) == 0) ? (SPI_PORT_OUT | BIT4) : (SPI_PORT_OUT & ~BIT4); }
 117  
 118  
 119  /**
 120  
 121  
 122   **/
 123  #define SPI_write(data) \
 124    { SPI_TX_BUF = (data); \
 125      while (SPI_BUSY) WDG_reset(); /*cekat dokud neni vysilaci buffer prazdny*/ \
 126    }
 127  
 128  #endif /* _SPI_H_ */
 129  
Zobrazeno: 731755x Naposledy: 29.11.2022 06:06:23