Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / mcu / libfitkit /

fpga.h

   1  /*******************************************************************************
   2     fpga.h:
   3     Copyright (C) 2006 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42  *******************************************************************************/
  43  #ifndef _FPGA_H_
  44  #define _FPGA_H_
  45  
  46  #define OC_FPGA 0x10   ///< baze OC pro FPGA (platne jsou horni 4 bity)
  47  
  48  #define SPI_FPGA_ENABLE_WRITE 0x01   ///< Definice bitu reprezentujici zapis do FPGA
  49  #define SPI_FPGA_ENABLE_READ  0x02   ///< Definice bitu reprezentujici cteni z FPGA
  50  
  51  
  52  /******************************************************************************/
  53  /* reset pro FPGA */
  54  #define FPGA_RESET_OUT    P3OUT
  55  #define FPGA_RESET_DIR    P3DIR
  56  #define FPGA_RESET_PIN    BIT0               ///< signal RESET pro komponenty uvnitr FPGA
  57  
  58  
  59  /**
  60   \brief Inicializace resetu pro FPGA
  61   **/
  62  void FPGA_init(void);
  63  
  64  
  65  /**
  66   \brief Reset FPGA.
  67   */
  68  void FPGA_reset(void);
  69  
  70  
  71  /**
  72  
  73   **/
  74  #define FPGA_Close()  SPI_Close()
  75  
  76  /**
  77  
  78  
  79  
  80  
  81  
  82  
  83  
  84   **/
  85  int FPGA_SPI_RW_AN_DN(unsigned char rw, unsigned long addr, unsigned char *data,
  86                        unsigned char an, unsigned char dn);
  87  
  88  /**
  89  
  90   \param rw - povoleni cteni a (nebo) zapisu (SPI_FPGA_ENABLE_WRITE, SPI_FPGA_ENABLE_READ)
  91  
  92  
  93  
  94  
  95   **/
  96  int FPGA_SPI_RW_A8_DN(unsigned char rw, unsigned char addr, unsigned char *data,
  97                        int n);
  98  
  99  /**
 100  
 101  
 102  
 103  
 104  
 105   **/
 106  unsigned char FPGA_SPI_RW_A8_D8(unsigned char rw, unsigned char addr,
 107                                  unsigned char data);
 108  
 109  /**
 110  
 111  
 112  
 113  
 114  
 115   **/
 116  unsigned int FPGA_SPI_RW_A8_D16(unsigned char rw, unsigned char addr,
 117                                  unsigned int data);
 118  
 119  #endif /* _FPGA_H_ */
 120  
Zobrazeno: 731765x Naposledy: 29.11.2022 06:34:14