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fpga.c

   1  /*******************************************************************************
   2     fpga.c:
   3     Copyright (C) 2006 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42  *******************************************************************************/
  43  
  44  #include <string.h>
  45  #include "arch_specific.h"
  46  #include "fitkitlib.h"
  47  #include "define.h"
  48  #include "globfun.h"
  49  #include "uart.h"
  50  #include "flash_fpga.h"
  51  #include "spi.h"
  52  #include "fpga.h"
  53  #include "timer_b.h"
  54  
  55  /******************************************************************************/
  56  /* Operacni kody FPGA */
  57  
  58  
  59  /**
  60   \brief Inicializace resetu pro FPGA
  61   **/
  62  void FPGA_init(void) {
  63  
  64    FPGA_RESET_DIR |= FPGA_RESET_PIN;
  65    FPGA_RESET_OUT |= FPGA_RESET_PIN;
  66  }
  67  
  68  
  69  /**
  70   \brief Reset FPGA.
  71   */
  72  void FPGA_reset(void){
  73    FPGA_RESET_OUT |= FPGA_RESET_PIN;
  74    delay_cycle(100);
  75    FPGA_RESET_OUT &= ~FPGA_RESET_PIN;
  76  
  77    //cekani na nabehnuti oscilatoru
  78    delay_ms(500);
  79  }
  80  
  81  
  82  /**
  83  
  84  
  85  
  86  
  87  
  88   **/
  89  unsigned char FPGA_SPI_RW_A8_D8(unsigned char rw, unsigned char addr,
  90                                  unsigned char data) {
  91    unsigned char data_out;
  92    SPI_set_cs_FPGA(1);
  93    // zapis op. kodu
  94    SPI_read_write(OC_FPGA|rw);
  95    // zapis adresy
  96    SPI_read_write(addr);
  97    // zapis a cteni dat
  98    data_out = SPI_read_write(data);
  99    SPI_set_cs_FPGA(0);
 100    return data_out;
 101  }
 102  
 103  /**
 104  
 105  
 106  
 107  
 108  
 109   **/
 110  unsigned int FPGA_SPI_RW_A8_D16(unsigned char rw, unsigned char addr,
 111                                  unsigned int data) {
 112    unsigned char data_inL, data_inH;
 113    unsigned int data_out;
 114    data_inL = data & 0xFF;
 115    data_inH = (data >> 8) & 0xFF;
 116    SPI_set_cs_FPGA(1);
 117    // zapis op. kodu
 118    SPI_read_write(OC_FPGA|rw);
 119    // zapis adresy
 120    SPI_read_write(addr);
 121    // zapis a cteni dat
 122    data_out = SPI_read_write(data_inH) << 8;
 123    data_out = data_out + SPI_read_write(data_inL);
 124    SPI_set_cs_FPGA(0);
 125    return data_out;
 126  }
 127  
 128  
 129  
 130  /**
 131  
 132   \param rw - povoleni cteni a (nebo) zapisu (SPI_FPGA_ENABLE_WRITE, SPI_FPGA_ENABLE_READ)
 133  
 134  
 135  
 136  
 137   **/
 138  int FPGA_SPI_RW_A8_DN(unsigned char rw, unsigned char addr, unsigned char *data,
 139                        int n) {
 140    int i;
 141    SPI_set_cs_FPGA(1);
 142    // zapis op. kodu
 143    SPI_read_write(OC_FPGA|rw);
 144    // zapis adresy
 145    SPI_read_write(addr);
 146    //zapis dat
 147    if ((rw & SPI_FPGA_ENABLE_READ) == SPI_FPGA_ENABLE_READ) {
 148       // zapis a cteni dat
 149       for (i = 0; i < n; i++)
 150           data[i] = SPI_read_write(data[i]);
 151    } else {
 152       // zapis dat
 153       for (i = 0; i < n; i++)
 154           SPI_read_write(data[i]);
 155    }
 156    SPI_set_cs_FPGA(0);
 157    return 0;
 158  }
 159  
 160  
 161  /**
 162  
 163  
 164  
 165  
 166  
 167  
 168  
 169   **/
 170  int FPGA_SPI_RW_AN_DN(unsigned char rw, unsigned long addr, unsigned char *data,
 171                        unsigned char an, unsigned char dn) {
 172    int i;
 173    SPI_set_cs_FPGA(1);
 174    // zapis op. kodu
 175    SPI_read_write(OC_FPGA | rw);
 176    // zapis adresy
 177    for (i = an-1; i >= 0; i--)
 178      SPI_read_write((unsigned char)((addr >> (i*8)) & 0xFF));
 179  
 180    if ((rw & SPI_FPGA_ENABLE_READ) == SPI_FPGA_ENABLE_READ) {
 181       // zapis a cteni dat
 182       for (i = 0; i < dn; i++)
 183           data[i] = SPI_read_write(data[i]);
 184    } else {
 185       // zapis dat
 186       for (i = 0; i < dn; i++)
 187           SPI_read_write(data[i]);
 188    }
 189    SPI_set_cs_FPGA(0);
 190    return 0;
 191  }
 192  
Zobrazeno: 731719x Naposledy: 29.11.2022 04:24:19