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flash_fpga.c

   1  /*******************************************************************************
   2     flash_fpga.c:
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42     Popis:
  43       Sdileny ovladac pro flash pamet and FPGA SpartanIII.
  44  *******************************************************************************/
  45  
  46  #include "arch_specific.h"
  47  #include "define.h"
  48  #include "flash_fpga.h"
  49  #include "uart.h"
  50  #include "spi.h"
  51  
  52  // SPI rozhrani a SpartanII
  53  
  54  
  55  
  56  
  57  #define DONE        BIT7        ///< DONE vstup do FPGA
  58  
  59  
  60  
  61  // port SPI a SpartanII
  62  #define FLPORTDIR   P5DIR       ///< direct port
  63  
  64  
  65  
  66  
  67  /**
  68  
  69   **/
  70  
  71  void delay_cycle_(unsigned int delay) {
  72    volatile unsigned int ii;
  73    for (ii=0; ii<delay; delay++) {
  74      WDG_reset();
  75    }
  76  }
  77  
  78  /**
  79  
  80   **/
  81  void FPGAConfig_init(void) {
  82    // #FPROG jako otevreny kolektor, pri inicializaci v HiZ
  83    P4OUT |= PROGn;               // jenom vnitrni priznak v MCU
  84    P4DIR &= ~PROGn;              // #FPROG jako vstup, HiZ stav
  85    // FDONE jako vstup
  86    P4DIR &= ~DONE;               // FDONE vstup
  87    // FINITn jako vstup
  88    P5DIR &= ~INITn;              // FINIT vstup
  89  }
  90  
  91  /**
  92  
  93  
  94  
  95   **/
  96  unsigned char FPGAConfig_initialize(void) {
  97    // #FPROG do 0
  98    P4OUT &= ~PROGn;              // jenom vnitrni priznak v MCU
  99    P4DIR |= PROGn;               // #FPROG jako vystup do 0
 100    P4OUT &= ~PROGn;              // #FPROG do 0
 101    delay_cycle_(100);                 // zpozdeni
 102    P4DIR &= ~PROGn;              // #FPROG do HiZ (do 1)
 103  
 104    P5DIR &= ~INITn;              // FINITn jako vstup
 105  
 106    if ((P5IN & INITn) != 0) {    // #INIT neni v nule
 107      term_send_str_crlf("#INIT neni v 0 po #PROG inicializaci FPGA");
 108      return 0;
 109    }
 110    if ((P4IN & DONE) != 0) {     // DONE neni v 0
 111      term_send_str_crlf("DONE neni v 0 po #PROG inicializaci FPGA");
 112      return 0;
 113    }
 114    delay_cycle_(100);                // zpozdeni minimalne 100us
 115    if ((P5IN & INITn) == 0) {    // #INIT neni v 1
 116      term_send_str_crlf("#INIT neni v 1 po vynulovani FPGA");
 117      return 0;
 118    }
 119  
 120    return 1;                     // inicializace v poradku, cekani na nacteni dat
 121  }
 122  
 123  /**
 124  
 125  
 126  
 127   **/
 128  unsigned char FPGAConfig_finalize(void) {
 129    delay_cycle_(100);                // zpozdeni
 130    if ((P4IN & DONE) == 0) {    // DONE neni v 1
 131      term_send_str_crlf("DONE neni v  1 po programovani FPGA");
 132      return 0;
 133    }
 134  
 135    P5DIR |= INITn;      // FINITn jako vystup
 136    return 1;            // inicializace v poradku, cekani na nacteni dat
 137  }
 138  
 139  /**
 140   \brief Detekce FPGA (hack).
 141   \return 0 - FPGA neodpovida zvolenemu IDcode
 142          \n 1 - FPGA odpovida zvolenemu IDcode
 143   **/
 144  unsigned char FPGAConfig_detect_fpga(unsigned long idcode)
 145  {
 146    int il;
 147    unsigned char detected;
 148  
 149    if (FPGAConfig_initialize() == 0) {
 150      return 0;
 151    }
 152  
 153    SPI_read_wait_write(0xFF); SPI_read_wait_write(0xFF); SPI_read_wait_write(0xFF); SPI_read_wait_write(0xFF); //dummy
 154    SPI_read_wait_write(0xAA); SPI_read_wait_write(0x99); SPI_read_wait_write(0x55); SPI_read_wait_write(0x66); //sync
 155  /*
 156    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 157    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x07); //RCRC
 158  */
 159    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x60); SPI_read_wait_write(0x01); //flr
 160    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x0F); //len (words)
 161    // XC3S50  - FLR=24
 162  
 163    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x20); SPI_read_wait_write(0x01); //cor
 164    SPI_read_wait_write(0x40); SPI_read_wait_write(0x00); SPI_read_wait_write(0x3F); SPI_read_wait_write(0xE5); //enable crc
 165  
 166    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0xC0); SPI_read_wait_write(0x01); //idcode write
 167    SPI_read_wait_write(idcode >> 24); SPI_read_wait_write((idcode >> 16) & 0xFF); SPI_read_wait_write((idcode >> 8) & 0xFF); SPI_read_wait_write(idcode & 0xFF);
 168  
 169  /*
 170    SPI_read_wait_write(0x30); SPI_read_wait_write(0x00); SPI_read_wait_write(0xC0); SPI_read_wait_write(0x01); //mask
 171    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00);
 172  
 173    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 174  
 175    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 176    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x09); //SWITCH
 177  
 178    SPI_read_wait_write(0x30); SPI_read_wait_write(0x00); SPI_read_wait_write(0x20); SPI_read_wait_write(0x01); //far
 179    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00);
 180    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 181  */
 182  
 183    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 184    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x01); //WCFG
 185  
 186  //  term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 187  
 188    SPI_read_wait_write(0x30); SPI_read_wait_write(0x00); SPI_read_wait_write(0x40); SPI_read_wait_write(0x10); //write fdri 44 words
 189  for (il=0;il<0x10;il++) {
 190    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00);
 191  }
 192    detected = FPGAConfig_INITn() > 0;
 193  
 194    //abort
 195    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 196    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x03); //LFRM
 197  
 198  /*
 199    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 200    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x0A); //GRESTORE
 201  
 202    term_send_str("E");
 203    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 204    */
 205  /*
 206  
 207    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 208    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x03); //LFRM
 209  
 210    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 211  */
 212  /*
 213  for (il=0;il<50;il++) {
 214    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 215    SPI_read_wait_write(0x20); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); //nop
 216  }
 217  
 218    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 219    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x05); //START
 220  
 221    SPI_read_wait_write(0x30); SPI_read_wait_write(0x00); SPI_read_wait_write(0xA0); SPI_read_wait_write(0x01); //CTL
 222    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00);
 223  
 224    SPI_read_wait_write(0x30); SPI_read_wait_write(0x01); SPI_read_wait_write(0x80); SPI_read_wait_write(0x01); //cmd
 225    SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x0D); //DESYNCH
 226  
 227  term_send_str("G");
 228  for (il=0;il<50;il++) {
 229    term_send_num(FPGAConfig_DONE()); term_send_str(","); term_send_num(FPGAConfig_INITn()); term_send_str(",");
 230    SPI_read_wait_write(0x20); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); SPI_read_wait_write(0x00); //nop
 231  }
 232  */
 233  
 234    P5DIR |= INITn;  // FINITn jako vystup
 235  
 236    return detected != 0;
 237  }
 238  
 239  
Zobrazeno: 731766x Naposledy: 29.11.2022 06:36:31