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fitkitlib.c

   1  /*******************************************************************************
   2     fitkitlib.c:
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42     Popis:
  43  
  44  *******************************************************************************/
  45  
  46  #include <math.h>
  47  #include <stdio.h>
  48  #include "arch_specific.h"
  49  #include "define.h"
  50  #include "globfun.h"
  51  #include "timer_b.h"
  52  #include "uart.h"
  53  #include "cmd.h"
  54  #include "flash_fpga.h"
  55  #include "flash.h"
  56  #include "terminal.h"
  57  #include "fpga.h"
  58  #include "spi.h"
  59  #include "fitkitlib.h"
  60  
  61  //#include "xmodem.h"
  62  #include "filetransfer.h"
  63  
  64  unsigned long FPGA_config_length = 54908;
  65  
  66  /**
  67  
  68  
  69   **/
  70  void delay_cycle(unsigned int delay) {
  71    volatile unsigned int i = 0;
  72  
  73    while (1) {
  74       if (i == delay) return;
  75       i++;
  76    }
  77  }
  78  
  79  
  80  /**
  81   \brief Inicializace a nastaveni hodin pro MCU a FPGA
  82  
  83   **/
  84  int clock_system_init(void) {
  85    WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT
  86  
  87    #if defined MSP_16X
  88      /// pocatecni nastaveni hodin
  89      BCSCTL1 = RSEL2 + RSEL1 + RSEL0;      /// nizka frekvence na LFXT1, vys. fr. na LFXT2
  90                                            /// DCO na 3.0MHz, ACLK na 32.768kHz
  91      /// nabeh krystalovych oscilatoru
  92      _BIC_SR(OSCOFF);                      /// nulovani OscOFF, povoleni LFXT1
  93      do {
  94        IFG1 &= ~OFIFG;                     /// nulovani OFIFG
  95        delay_cycle(1000);                         /// zpozdeni
  96      } while ((IFG1 & OFIFG) != 0);        /// test nabehnuti oscilatoru LFXT1 a LFXT2
  97    //  delay_cycle(0);                           /// zpozdeni
  98  
  99      BCSCTL2 = SELM_2 + SELS;              /// SMCLK = LFXT2 = 7.3728 MHz, MCLK = LFXT2 = 7.3728 MHz
 100    #elif defined MSP_261X
 101      BCSCTL1 &= ~XT2OFF;                       // Activate XT2 high freq xtal
 102  
 103  
 104      // Wait for xtal to stabilize
 105      _BIC_SR(OSCOFF);                      /// nulovani OscOFF, povoleni LFXT1
 106      do
 107      {
 108        IFG1 &= ~OFIFG;                           // Clear OSCFault flag
 109        delay_cycle(1000);
 110      } while ((IFG1 & OFIFG));                   // OSCFault flag still set?
 111  
 112      BCSCTL2 = SELM_2 | SELS | DIVM_0 | DIVS_1;   // MCLK = XT2CLK = 14.745 MHz, SMCLK = XT2CLK/2 = 7.3728 MHz
 113    #else
 114      #error "Can't initialize clock system"
 115    #endif
 116  
 117    /// INICIALIZACE vystupu hodin pro FPGA
 118    P5DIR |= SMCLK + ACLK;         // nastavi piny jako vystupni
 119    P5SEL |= SMCLK;                ///< pripoji SMCLK na pin
 120  
 121    return 0;
 122  }
 123  
 124  /**
 125   \brief Odpojeni SMCLK vedouciho do FPGA
 126  **/
 127  void smclk_stop(void) {
 128    FPGA_RESET_DIR |= FPGA_RESET_PIN;
 129    FPGA_RESET_OUT |= FPGA_RESET_PIN;
 130    P5DIR |= SMCLK;         // nastavi pin jako vystupni
 131    P5OUT &= ~SMCLK;        // na vystup 0
 132    P5SEL &= ~SMCLK;        // odpojit od hodinoveho signalu
 133  }
 134  
 135  /**
 136   \brief Nakonfiguruje FPGA pomoci dat ulozenych ve FLASH pameti
 137   \return 0 - chyba
 138          \n jinak - bez chyby
 139   **/
 140  char fpga_configure_from_flash(void) {
 141    term_send_str("Programovani FPGA: ");
 142  
 143    // test, zda-li jsou ve FLASH platna data
 144    if (FLASH_isPageBlank(FLASH_FPGA_BIN_PAGE) != 0) {
 145      term_send_str_crlf("neuspesne - chybi data ve FLASH");
 146      return 0; // chyba
 147    }
 148  
 149    // programovani FPGA
 150    if (FLASH_ProgFPGA(FLASH_FPGA_BIN_ADDRESS, FPGA_config_length) == 0) {
 151      term_send_str_crlf("neuspesne - chybne FPGA");
 152      return 0;
 153    }
 154  
 155    term_send_str_crlf(" OK");
 156  
 157    term_send_str_crlf("Inicializace HW");
 158  
 159    FPGA_reset(); // reset FPGA
 160    fpga_initialized(); // uzivatelska inicializace
 161  
 162    return 1; // OK
 163  }
 164  
 165  /**
 166   \brief Nakonfiguruje FPGA pomoci dat poslanych pres terminal
 167   \return 0 - chyba
 168          \n jinak - bez chyby
 169   **/
 170  char fpga_configure_from_mcu(void) {
 171  
 172    term_send_str("Programovani FPGA: ");
 173  
 174    // inicializace FPGA SpartanII pro programovani
 175    if (FPGAConfig_initialize() == 0) {
 176      term_send_str_crlf("neuspesne - FPGA se neporadilo inicializovat");
 177      return  0; // chybna inicializace
 178    }
 179  
 180    #ifdef XMODEMAPI
 181    XModemProgFPGA();
 182    #else
 183    SPI_WriteFile("FPGA configuration","*.bin", FPGA_config_length);
 184    #endif
 185  
 186    // ukonceni programovani FPGA SpartanIII a kontrola chyb
 187    if (FPGAConfig_finalize() == 0) {
 188      term_send_str_crlf("neuspesne - chybne FPGA");
 189      return 0;
 190    }
 191  
 192    term_send_str_crlf(" OK");
 193  
 194    term_send_str_crlf("Inicializace HW");
 195    FPGA_reset(); // reset FPGA
 196    fpga_initialized(); // uzivatelska inicializace
 197  
 198    return 1;
 199  }
 200  
 201  //////////////////////////////////////////////////////////////////////////////
 202  // inicializace MCU
 203  
 204  /**
 205  
 206   \param progfpga - je-li 1, provede se naprogramovani FPGA z FLASH
 207  
 208   **/
 209  int initialize_hardware_(char progfpga) {
 210     clock_system_init();   ///< Inicializace a nastaveni hodin pro MCU a FPGA
 211  
 212     timerb_init();  /// inicializace casovace, pro funkci delay_ms()
 213  
 214     FPGA_init();    ///<  Inicializace resetu pro FPGA
 215  
 216     WDG_init();             ///< init softwaroveho watchdogu
 217     _EINT();                 ///< povoleni preruseni
 218  
 219     terminal_init(); /// inicializace seriove linky
 220  
 221     SPI_Init();            // SPI inicializace
 222  
 223     term_send_str("Inicializace FPGA: ");
 224     if (FPGAConfig_detect_fpga(0x0140D093))
 225     {
 226         FPGA_config_length = 54908;
 227         term_send_str_crlf("XC3S50")
 228     }
 229     else if (FPGAConfig_detect_fpga(0x0141C093))
 230     {
 231         FPGA_config_length = 212392;
 232         term_send_str_crlf("XC3S400")
 233     }
 234     else if (FPGAConfig_detect_fpga(0x01414093))
 235     {
 236         FPGA_config_length = 130952;
 237         term_send_str_crlf("XC3S200")
 238     }
 239     else
 240         term_send_str_crlf("nezname FPGA");
 241  
 242     if (flash_init(1)) //Inicializace FLASH, vypis informaci
 243     {
 244  
 245        FPGAConfig_init();
 246        ///Programovani FPGA
 247        if (progfpga)
 248           fpga_configure_from_flash();
 249     }
 250  
 251     term_send_str(">");
 252     return 0;
 253  }
 254  /**
 255  
 256  
 257   **/
 258  int initialize_hardware(void) {
 259    return initialize_hardware_(1);
 260  }
 261