Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / mcu / libfitkit /

define.h

   1  /*******************************************************************************
   2     define.h:
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5  
   6     LICENSE TERMS
   7  
   8     Redistribution and use in source and binary forms, with or without
   9     modification, are permitted provided that the following conditions
  10     are met:
  11     1. Redistributions of source code must retain the above copyright
  12        notice, this list of conditions and the following disclaimer.
  13     2. Redistributions in binary form must reproduce the above copyright
  14        notice, this list of conditions and the following disclaimer in
  15        the documentation and/or other materials provided with the
  16        distribution.
  17     3. All advertising materials mentioning features or use of this software
  18        or firmware must display the following acknowledgement:
  19  
  20          This product includes software developed by the University of
  21          Technology, Faculty of Information Technology, Brno and its
  22          contributors.
  23  
  24     4. Neither the name of the Company nor the names of its contributors
  25        may be used to endorse or promote products derived from this
  26        software without specific prior written permission.
  27  
  28     This software or firmware is provided ``as is'', and any express or implied
  29     warranties, including, but not limited to, the implied warranties of
  30     merchantability and fitness for a particular purpose are disclaimed.
  31     In no event shall the company or contributors be liable for any
  32     direct, indirect, incidental, special, exemplary, or consequential
  33     damages (including, but not limited to, procurement of substitute
  34     goods or services; loss of use, data, or profits; or business
  35     interruption) however caused and on any theory of liability, whether
  36     in contract, strict liability, or tort (including negligence or
  37     otherwise) arising in any way out of the use of this software, even
  38     if advised of the possibility of such damage.
  39  
  40     $Id$
  41  
  42     Popis:
  43       Definice preprocesoru
  44  *******************************************************************************/
  45  
  46  #ifndef _DEFINE_H_
  47  #define _DEFINE_H_
  48  
  49  #include "arch_specific.h"
  50  
  51  #define SPIMAX
  52  #define IDKIT "FITkit "     // Identifikace FITkitu
  53  #define IDREV "$Rev: 163 $" // Revize z SVN
  54  
  55  #if defined MSP_16X
  56    #define IDFLG "1.x "
  57  #elif defined MSP_261X
  58    #define IDFLG "2.x "
  59  #else
  60    #error "Unknown CPU type"
  61  #endif
  62  
  63  /*
  64   * #ifdef SPIMAX
  65    #define IDFLG "SPImax "   // Nastavena max. frekvence SPI
  66  #else
  67    #define IDFLG ""
  68  #endif
  69  */
  70  
  71  #define ID_KIT_STRING (IDKIT IDFLG IDREV)     ///< Identifikacni string FITKitu
  72  
  73  
  74  /******************************************************************************/
  75  /* Seriova linka UART */
  76  #define B_921600        3               /* baud rychlosti */
  77  #define B_460800        2
  78  #define B_230400        1
  79  #define B_115200        0
  80  #define B_57600         57600
  81  #define B_38400         38400
  82  #define B_19200         19200
  83  #define B_9600          9600
  84  #define B_4800          4800
  85  #define B_2400          2400
  86  #define B_1200          1200
  87  
  88  /* Defaultni rychlost seriove linky po inicializaci MCU */
  89  #define B_default       B_460800
  90  
  91  
  92  /******************************************************************************/
  93  /* Seriova Flash pamet */
  94  
  95  #define BUFFER_SIZE       264       ///< velikost stranky buffru [byte]
  96  #define PAGE_SIZE         264       ///< velikost stranky [byte]
  97  #define CNT_PAGES_IN_BLOCK 8        ///< pocet stranek v bloku
  98  #define BLOCK_SIZE   CNT_PAGES_IN_BLOCK * PAGE_SIZE ///< velikost bloku [byte]
  99  
 100  /* adresovy prostor Flash pameti */
 101  /*   - nulta stranka nevyuzita - informace pro FKFlash (checksum HEX, BIN) */
 102  /*   - stranka 8 - 215 data pro FPGA (XC3S50 - max 54 908B) */
 103  /*   - stranka 8 - 815 data pro FPGA (XC3S400 - max 212 392B), zarovnano na nasobky 8 */
 104  
 105  #define FLASH_FPGA_BIN_PAGE 8 ///< pocatecni adresa (cislo stranky) FPGA dat
 106  #define FLASH_FPGA_BIN_ADDRESS (FLASH_FPGA_BIN_PAGE*PAGE_SIZE)
 107  #define FPGA_BIN_PAGES (((unsigned long)(FPGA_config_length) + PAGE_SIZE-1) / PAGE_SIZE)
 108  #define FLASH_USER_DATA_PAGE (FLASH_FPGA_BIN_PAGE + (((FPGA_BIN_PAGES) >> 3) << 3)) //zarovnano na velikost bloku (8 stranek)
 109  #define FLASH_USER_DATA_ADDRESS ((FLASH_USER_DATA_PAGE)*PAGE_SIZE)
 110  
 111  /******************************************************************************/
 112  /* Zvlastni znaky */
 113  #define BS              0x08            ///< BackSpace
 114  #define CR              0x0D            ///< CR
 115  #define LF              0x0A            ///< LF
 116  #define ESC             0x1B            ///< ESC
 117  #define ERS_CHAR        0xFF            ///< znak, kterym se maze flash
 118  
 119  
 120  /******************************************************************************/
 121  /* Hodinove vystupy */
 122  
 123  /* ACLK vystup - 32.768kHz */
 124  #define ACLK            BIT6            ///< ACLK pin
 125  
 126  /* SMCLK vystup - 7.3728MHz */
 127  #define SMCLK           BIT5            ///< SMCLK pin
 128  
 129  
 130  /******************************************************************************/
 131  /* LED vystupy */
 132  #define LED0            BIT0            ///< LED D5
 133  #define LED1            BIT7            ///< LED D6
 134  
 135  #define set_led_d5(on) {\
 136    P1DIR |= LED0; /* nastavit bit jako vystup */ \
 137    P1OUT = (on) ? (P1OUT & ~LED0) : (P1OUT | LED0); /* 0 - sviti, 1 - nesviti */ \
 138    }
 139  
 140  #define set_led_d6(on) {\
 141    P5DIR |= LED1; /* nastavit bit jako vystup */ \
 142    P5OUT = (on) ? (P5OUT & ~LED1) : (P5OUT | LED1); /* 0 - sviti, 1 - nesviti */ \
 143    }
 144  
 145  #define flip_led_d5() {P1OUT ^= LED0;}
 146  #define flip_led_d6() {P5OUT ^= LED1;}
 147  
 148  
 149  /******************************************************************************/
 150  /* Adresovy prostor MCU */
 151  #define MCU_RAM_START   0x0200          ///< MCU
 152  #define MCU_RAM_END     0x09FF
 153  
 154  
 155  /******************************************************************************/
 156  /* Watchdog */
 157  
 158  /* Povoleni/zakaz watchdogu */
 159  //#define WDG_ENABLE
 160  
 161  
 162  /* pokud je definovan WDG */
 163  #ifdef  WDG_ENABLE                      // watchdog
 164  
 165    #define WDG_init() \
 166      { WDTCTL = WDTPW + WDTCNTCL + WDTIS0;    /* SW watchdog na SMCLK, (8.9ms interval) */ \
 167        WDG_reset(); \
 168      }
 169  
 170    /* musi se aktivovat casteji nez 8.9ms, jinak dojde k resetu MCU */
 171    #define WDG_reset() \
 172      { WDTCTL = WDTPW + WDTCNTCL + WDTIS0;  \
 173        if ((IFG1 & OFIFG) != 0) { _DINT(); WDTCTL = 0; while (1) {}; } \
 174      }
 175  
 176  #else
 177  
 178    #define WDG_init()
 179    #define WDG_reset()
 180  
 181  #endif /* WDG_ENABLE */
 182  
 183  #define WDG_stop()      WDTCTL = WDTPW + WDTHOLD;             ///< stop WDT
 184  
 185  
 186  /******************************************************************************/
 187  /* Terminal */
 188  
 189  /* Maximalni delka retezce z terminalu */
 190  #define  MAX_COMMAND_LEN   24
 191  
 192  /* Makra strcmpN na porovnani retezcu delky N */
 193  #define  strcmp1(a, b)  (*(a) == *(b))
 194  #define  strcmp2(a, b)  (strcmp1(a, b) && strcmp1(a+1, b+1))
 195  #define  strcmp3(a, b)  (strcmp1(a, b) && strcmp2(a+1, b+1))
 196  #define  strcmp4(a, b)  (strcmp1(a, b) && strcmp3(a+1, b+1))
 197  #define  strcmp5(a, b)  (strcmp1(a, b) && strcmp4(a+1, b+1))
 198  #define  strcmp6(a, b)  (strcmp1(a, b) && strcmp5(a+1, b+1))
 199  #define  strcmp7(a, b)  (strcmp1(a, b) && strcmp6(a+1, b+1))
 200  #define  strcmp8(a, b)  (strcmp1(a, b) && strcmp7(a+1, b+1))
 201  #define  strcmp9(a, b)  (strcmp1(a, b) && strcmp8(a+1, b+1))
 202  #define  strcmp10(a, b) (strcmp1(a, b) && strcmp9(a+1, b+1))
 203  #define  strcmp11(a, b) (strcmp1(a, b) && strcmp10(a+1, b+1))
 204  #define  strcmp12(a, b) (strcmp1(a, b) && strcmp11(a+1, b+1))
 205  #define  strcmp13(a, b) (strcmp1(a, b) && strcmp12(a+1, b+1))
 206  #define  strcmp14(a, b) (strcmp1(a, b) && strcmp13(a+1, b+1))
 207  #define  strcmp15(a, b) (strcmp1(a, b) && strcmp14(a+1, b+1))
 208  #define  strcmp16(a, b) (strcmp1(a, b) && strcmp15(a+1, b+1))
 209  #define  strcmp17(a, b) (strcmp1(a, b) && strcmp16(a+1, b+1))
 210  #define  strcmp18(a, b) (strcmp1(a, b) && strcmp17(a+1, b+1))
 211  #define  strcmp19(a, b) (strcmp1(a, b) && strcmp18(a+1, b+1))
 212  #define  strcmp20(a, b) (strcmp1(a, b) && strcmp19(a+1, b+1))
 213  #define  strcmp21(a, b) (strcmp1(a, b) && strcmp20(a+1, b+1))
 214  #define  strcmp22(a, b) (strcmp1(a, b) && strcmp21(a+1, b+1))
 215  #define  strcmp23(a, b) (strcmp1(a, b) && strcmp22(a+1, b+1))
 216  #define  strcmp24(a, b) (strcmp1(a, b) && strcmp23(a+1, b+1))
 217  #define  strcmp25(a, b) (strcmp1(a, b) && strcmp24(a+1, b+1))
 218  #define  strcmp26(a, b) (strcmp1(a, b) && strcmp25(a+1, b+1))
 219  #define  strcmp28(a, b) (strcmp1(a, b) && strcmp27(a+1, b+1))
 220  #define  strcmp29(a, b) (strcmp1(a, b) && strcmp28(a+1, b+1))
 221  #define  strcmp30(a, b) (strcmp1(a, b) && strcmp29(a+1, b+1))
 222  #define  strcmp31(a, b) (strcmp1(a, b) && strcmp30(a+1, b+1))
 223  #define  strcmp32(a, b) (strcmp1(a, b) && strcmp31(a+1, b+1))
 224  
 225  
 226  /******************************************************************************/
 227  /* prikazy terminalu */
 228  #define PROG0                       10
 229  
 230  
 231  #define RST0                        20
 232  #define CMD_MCU_RESET           RST0+1  ///< reset MCU
 233  #define CMD_FPGA_RESET          RST0+2  ///< reset FPGA
 234  #define CMD_CLEARSCREEN         RST0+3  ///< clear screen (terminal reset)
 235  #define CMD_SMCLK_STOP          RST0+4  ///< stop SMCLK
 236  
 237  #define FL0                         30
 238  #define CMD_FLASH_FST            FL0
 239  
 240  
 241  
 242  
 243  
 244  
 245  
 246  
 247  
 248  
 249  
 250  
 251  
 252  
 253  
 254  
 255  
 256  #define CMD_FLASH_LAST           CMD_MCU_FLASHD_FPGA
 257  
 258  // prikazy pro FPGA
 259  /*
 260  #define FP0                         60
 261  #define CMD_FPGA_READ_B          FP0+0
 262  #define CMD_FPGA_READ_W          FP0+1
 263  #define CMD_FPGA_WRITE_B         FP0+2
 264  #define CMD_FPGA_WRITE_W         FP0+3
 265  */
 266  
 267  #define CMD_MCU_RAM_DUMP         249     ///< dump RAM/ROM pameti MCU
 268  
 269  
 270  
 271  
 272  
 273  /******************************************************************************/
 274  
 275  
 276  #endif /* _DEFINE_H_ */
 277  
Zobrazeno: 731763x Naposledy: 29.11.2022 06:31:42