Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / fpga / ctrls / audio /

aic23b_dsp_write.vhd

   1  -- top.vhd: Digital Audio Codec Transmitter Interface in DSP Communcation Mode
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Karel Slany <slany AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  use work.math_pack.all;
  49  
  50  -- digital audio sending unit
  51  -- the audio codec has to be configured to operate in DSP master mode
  52  entity aic23b_dsp_write is
  53    generic (
  54      DATA_WIDTH : integer := 16
  55    );
  56    port (
  57      -- Control signals
  58      CLK   : in std_logic;
  59      RST   : in std_logic;
  60      READY : out std_logic;
  61  
  62      -- DATA interface
  63      LIN      : in std_logic_vector(DATA_WIDTH-1 downto 0);
  64      RIN      : in std_logic_vector(DATA_WIDTH-1 downto 0);
  65      DATA_REQ : out std_logic;
  66  
  67      -- CODEC interface
  68      ALRCIN : in std_logic;
  69      ABCLK  : in std_logic;
  70      ADIN   : out std_logic
  71   );
  72  end entity aic23b_dsp_write;
  73  
  74  architecture basic of aic23b_dsp_write is
  75  
  76    -- ABCLK rising edge detector and sampler
  77    signal abclk_re : std_logic;
  78    signal abclk_last : std_logic_vector(1 downto 0);
  79    signal alrcin_last : std_logic;
  80  
  81    -- data to serializer
  82    signal data : std_logic_vector(DATA_WIDTH-1 downto 0);
  83  
  84    -- sample bit counter
  85    signal start_cntr : std_logic;
  86    signal bit_cntr : std_logic_vector(log2(DATA_WIDTH)-1 downto 0);
  87    signal bit_cntr_load : std_logic;
  88  
  89    -- output finite state machine
  90    type FSMstate is (SInit, SReadL, SWriteL, SReadR, SWriteR);
  91    signal pstate : FSMstate; -- actual state
  92    signal nstate : FSMstate; -- next state
  93    signal lread : std_logic;
  94    signal rread : std_logic;
  95    signal rotate : std_logic;
  96    signal output_en : std_logic;
  97  
  98  begin
  99  
 100    -- ABCLK rising edge detector and sampler
 101    abclk_re <= '1' when (abclk_last(1) = '0') and (abclk_last(0) = '1') else '0';
 102    abclk_detect_p : process (RST, CLK, ABCLK, ALRCIN)
 103    begin
 104      if (RST = '1') then
 105        abclk_last <= ABCLK & ABCLK;
 106        alrcin_last <= ALRCIN;
 107        --adin_last <= ADOUT;
 108      elsif (CLK'event) and (CLK = '1') then
 109        abclk_last <= abclk_last(0) & ABCLK;
 110        alrcin_last <= ALRCIN;
 111        --adin_last <= ADOUT;
 112      end if;
 113    end process abclk_detect_p;
 114  
 115    -- bit counter process
 116    start_cntr <= '1' when (abclk_re = '1') and (alrcin_last = '1') else '0';
 117    bit_cntr_load <= '1' when (bit_cntr = conv_std_logic_vector(DATA_WIDTH-1, log2(DATA_WIDTH))) else '0';
 118    bit_cntr_p : process (RST, CLK)
 119    begin
 120      if (RST = '1') then
 121        bit_cntr <= (others => '0');
 122      elsif (CLK'event) and (CLK = '1') then
 123        -- synchronous reset
 124        if (start_cntr = '1') then
 125          bit_cntr <= (others => '0');
 126        -- increase counter when sample ready
 127        -- abclk_re must be tested, signals may last several
 128        -- CLK but only one abclk_re
 129        elsif (abclk_re = '1') then
 130          if (bit_cntr_load = '1') then
 131            bit_cntr <= (others => '0');
 132          else
 133            bit_cntr <= bit_cntr + 1;
 134          end if;
 135        end if;
 136      end if;
 137    end process bit_cntr_p;
 138  
 139    -- present state process
 140    pstate_p : process (RST, CLK)
 141    begin
 142      if (RST = '1') then
 143        pstate <= SInit;
 144      elsif (CLK'event) and (CLK = '1') then
 145        pstate <= nstate;
 146      end if;
 147    end process pstate_p;
 148  
 149    -- next state logic, output driving
 150    nstate_p : process (pstate, start_cntr, abclk_re, bit_cntr_load)
 151    begin
 152      -- default values
 153      nstate <= SInit;
 154      lread <= '0';
 155      rread <= '0';
 156      rotate <= '0';
 157      output_en <= '1';
 158      READY <= '0';
 159      DATA_REQ <= '0';
 160  
 161      case pstate is
 162  
 163        when Sinit =>
 164          READY <= '1';
 165          output_en <= '0';
 166          if (start_cntr = '1') then
 167            nstate <= SReadL;
 168            lread <= '1';
 169            output_en <= '1';
 170          end if;
 171  
 172        when SreadL =>
 173          if (start_cntr = '1') then
 174            nstate <= SReadL;
 175            lread <= '1';
 176          else
 177            nstate <= SWriteL;
 178          end if;
 179  
 180        when SWriteL =>
 181          rotate <= '1';
 182          if (start_cntr = '1') then
 183            nstate <= SReadL;
 184            lread <= '1';
 185          -- abclk_re must be tested, signals may last several
 186          -- CLK but only one abclk_re
 187          elsif (abclk_re = '1') and (bit_cntr_load = '1') then
 188            nstate <= SReadR;
 189            rread <= '1';
 190          else
 191            nstate <= SWriteL;
 192          end if;
 193  
 194        when SReadR =>
 195          if (start_cntr = '1') then
 196            nstate <= SReadL;
 197            lread <= '1';
 198          else
 199            nstate <= SWriteR;
 200          end if;
 201  
 202        when SWriteR =>
 203          rotate <= '1';
 204          -- abclk_re must be tested, signals may last several
 205          -- CLK but only one abclk_re
 206          if (abclk_re = '1') and (bit_cntr_load = '1') then
 207            if (start_cntr = '1') then
 208              -- last sample can be written during next window anouncement
 209              nstate <= SReadL;
 210              lread <= '1';
 211              READY <= '1';
 212              DATA_REQ <= '1';
 213            else
 214              nstate <= SInit;
 215              output_en <= '0';
 216              READY <= '1';
 217              DATA_REQ <= '1';
 218            end if;
 219          elsif (start_cntr = '1') then
 220            nstate <= SReadL;
 221            lread <= '1';
 222          else
 223            nstate <= SWriteR;
 224          end if;
 225  
 226        when others => null;
 227  
 228      end case;
 229    end process nstate_p;
 230  
 231    -- output process
 232    ADIN <= data(DATA_WIDTH-1) when (output_en = '1') else '0';
 233    output_p : process (RST, CLK)
 234    begin
 235      if (RST = '1') then
 236        data <= (others => '0');
 237      elsif (CLK'event) and (CLK = '1') then
 238        if (lread = '1') then
 239          data <= LIN;
 240        elsif (rread = '1') then
 241          data <= RIN;
 242        elsif (rotate = '1') and (abclk_re = '1') then
 243          data <= data(DATA_WIDTH-2 downto 0) & data(DATA_WIDTH-1);
 244        end if;
 245      end if;
 246    end process output_p;
 247  
 248  end architecture basic;
 249  
Zobrazeno: 595874x Naposledy: 22.1.2022 10:29:21