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aic23b_dsp_ringbuffer.vhd

   1  -- top.vhd: Digital Audio Codec Ring Buffer, DSP mode
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Karel Slany <slany AT fit.vutbr.cz>
   5  --            Zdenek Vasicek <vasicek AT fit.vutbr.cz>
   6  --
   7  -- LICENSE TERMS
   8  --
   9  -- Redistribution and use in source and binary forms, with or without
  10  -- modification, are permitted provided that the following conditions
  11  -- are met:
  12  -- 1. Redistributions of source code must retain the above copyright
  13  --    notice, this list of conditions and the following disclaimer.
  14  -- 2. Redistributions in binary form must reproduce the above copyright
  15  --    notice, this list of conditions and the following disclaimer in
  16  --    the documentation and/or other materials provided with the
  17  --    distribution.
  18  -- 3. All advertising materials mentioning features or use of this software
  19  --    or firmware must display the following acknowledgement:
  20  --
  21  --      This product includes software developed by the University of
  22  --      Technology, Faculty of Information Technology, Brno and its
  23  --      contributors.
  24  --
  25  -- 4. Neither the name of the Company nor the names of its contributors
  26  --    may be used to endorse or promote products derived from this
  27  --    software without specific prior written permission.
  28  --
  29  -- This software or firmware is provided ``as is'', and any express or implied
  30  -- warranties, including, but not limited to, the implied warranties of
  31  -- merchantability and fitness for a particular purpose are disclaimed.
  32  -- In no event shall the company or contributors be liable for any
  33  -- direct, indirect, incidental, special, exemplary, or consequential
  34  -- damages (including, but not limited to, procurement of substitute
  35  -- goods or services; loss of use, data, or profits; or business
  36  -- interruption) however caused and on any theory of liability, whether
  37  -- in contract, strict liability, or tort (including negligence or
  38  -- otherwise) arising in any way out of the use of this software, even
  39  -- if advised of the possibility of such damage.
  40  --
  41  -- $Id$
  42  --
  43  --
  44  
  45  library ieee;
  46  use ieee.std_logic_1164.all;
  47  use ieee.std_logic_arith.all;
  48  use ieee.std_logic_unsigned.all;
  49  
  50  -- pragma translate_off
  51  library unisim;
  52  use unisim.vcomponents.all;
  53  -- pragma translate_on
  54  
  55  -- digital 16b audio transceiving unit
  56  -- the audio codec has to be configured to operate in DSP master mode
  57  entity aic23b_dsp_ringbuffer is
  58    port (
  59      -- Control signals
  60      RST : in std_logic;
  61      CLK : in std_logic;
  62      EN  : in std_logic;
  63  
  64      -- Ring Buffer interface
  65      BRAM_ADDR : in std_logic_vector(8 downto 0);
  66      BRAM_DOUT : out std_logic_vector(31 downto 0);
  67      BRAM_DIN  : in std_logic_vector(31 downto 0);
  68      BRAM_EN   : in std_logic;
  69      BRAM_WE   : in std_logic;
  70  
  71      ADDR_RD   : out std_logic_vector(8 downto 0);
  72      ADDR_WR   : out std_logic_vector(8 downto 0);
  73  
  74      -- CODEC digital interface
  75      ALRCOUT : in std_logic;
  76      ALRCIN  : in std_logic;
  77      ABCLK   : in std_logic;
  78      ADOUT   : in std_logic;
  79      ADIN    : out std_logic
  80    );
  81  end entity aic23b_dsp_ringbuffer;
  82  
  83  architecture basic of aic23b_dsp_ringbuffer is
  84  
  85    component aic23b_dsp_read
  86      generic (
  87        DATA_WIDTH : integer := 16
  88      );
  89      port (
  90        CLK        : in std_logic;
  91        RST        : in std_logic;
  92        ALRCOUT    : in std_logic;
  93        ABCLK      : in std_logic;
  94        ADOUT      : in std_logic;
  95        LOUT       : out std_logic_vector(DATA_WIDTH-1 downto 0);
  96        ROUT       : out std_logic_vector(DATA_WIDTH-1 downto 0);
  97        DATA_VALID : out std_logic
  98      );
  99    end component aic23b_dsp_read;
 100  
 101    component aic23b_dsp_write is
 102      generic (
 103        DATA_WIDTH : integer := 16
 104      );
 105      port (
 106        CLK     : in std_logic;
 107        RST     : in std_logic;
 108        ALRCIN  : in std_logic;
 109        ABCLK   : in std_logic;
 110        ADIN    : out std_logic;
 111        LIN     : in std_logic_vector(DATA_WIDTH-1 downto 0);
 112        RIN     : in std_logic_vector(DATA_WIDTH-1 downto 0);
 113        READY   : out std_logic;
 114        DATA_REQ: out std_logic
 115      );
 116    end component aic23b_dsp_write;
 117  
 118    component RAMB16_S36_S36
 119      port (
 120        DOA   : out std_logic_vector(31 downto 0); -- 32b output
 121        DOPA  : out std_logic_vector(3 downto 0);  -- 4b parity
 122        ADDRA : in std_logic_vector(8 downto 0);   -- address
 123        CLKA  : in std_ulogic;                     -- clock
 124        DIA   : in std_logic_vector(31 downto 0);  -- 32b input
 125        DIPA  : in std_logic_vector(3 downto 0);   -- 4b parity
 126        ENA   : in std_ulogic;                     -- enable read/write
 127        SSRA  : in std_ulogic;                     -- synchronous set/reset input
 128        WEA   : in std_logic;                      -- enable write input
 129  
 130        DOB   : out std_logic_vector(31 downto 0);
 131        DOPB  : out std_logic_vector(3 downto 0);
 132        ADDRB : in std_logic_vector(8 downto 0);
 133        CLKB  : in std_ulogic;
 134        DIB   : in std_logic_vector(31 downto 0);
 135        DIPB  : in std_logic_vector(3 downto 0);
 136        ENB   : in std_ulogic;
 137        SSRB  : in std_ulogic;
 138        WEB   : in std_logic
 139      );
 140    end component RAMB16_S36_S36;
 141  
 142    signal sample_in     : std_logic_vector(31 downto 0);
 143    signal sample_valid  : std_logic;
 144    signal sample_out    : std_logic_vector(31 downto 0);
 145    signal sample_req    : std_logic;
 146    signal bram_out      : std_logic_vector(31 downto 0);
 147  
 148    signal wr_cntr      : std_logic_vector(8 downto 0);
 149    signal rd_cntr      : std_logic_vector(8 downto 0);
 150    signal addr         : std_logic_vector(8 downto 0);
 151    signal serialout    : std_logic;
 152  
 153  begin
 154  
 155    -- read unit (receiver)
 156    aud_rd : aic23b_dsp_read
 157       generic map (
 158         DATA_WIDTH => 16
 159       )
 160       port map (
 161         CLK     => CLK,
 162         RST     => RST,
 163         ALRCOUT => ALRCOUT,
 164         ABCLK   => ABCLK,
 165         ADOUT   => ADOUT,
 166         LOUT    => sample_in(31 downto 16),
 167         ROUT    => sample_in(15 downto 0),
 168         DATA_VALID => sample_valid
 169       );
 170  
 171    -- write unit (transmitter)
 172    aud_wr : aic23b_dsp_write
 173       generic map (
 174         DATA_WIDTH => 16
 175       )
 176       port map (
 177         CLK    => CLK,
 178         RST    => RST,
 179         READY  => open,
 180         ALRCIN => ALRCIN,
 181         ABCLK  => ABCLK,
 182         ADIN   => serialout,
 183         LIN    => sample_out(31 downto 16),
 184         RIN    => sample_out(15 downto 0),
 185         DATA_REQ  => sample_req
 186       );
 187  
 188    ADIN <= serialout and EN;
 189  
 190    -- ring buffer (512 x 32bit items)
 191    bram : RAMB16_S36_S36
 192       port map (
 193         DOA   => bram_out,
 194         DOPA  => open,
 195         ADDRA => addr,
 196         CLKA  => CLK,
 197         DIA   => sample_in,
 198         DIPA  => (others => '0'),
 199         ENA   => '1',
 200         SSRA  => '0',
 201         WEA   => sample_valid,
 202  
 203         DOB   => BRAM_DOUT,
 204         DOPB  => open,
 205         ADDRB => BRAM_ADDR,
 206         CLKB  => CLK,
 207         DIB   => BRAM_DIN,
 208         DIPB  => (others => '0'),
 209         ENB   => BRAM_EN,
 210         SSRB  => '0',
 211         WEB   => BRAM_WE
 212       );
 213  
 214    -- write enable and increase write address counter
 215    addr_wr_cntr : process (RST, CLK)
 216    begin
 217      if (RST = '1') then
 218        wr_cntr <= (others => '0');
 219      elsif (CLK'event) and (CLK = '1') then
 220        if (sample_valid = '1') then
 221          if (EN = '1') then
 222            wr_cntr <= wr_cntr + 1;
 223          end if;
 224        end if;
 225      end if;
 226    end process;
 227  
 228    ADDR_WR <= wr_cntr;
 229  
 230    -- multiplexed address input and read from bram
 231    addr <= wr_cntr when (sample_valid = '1') else rd_cntr;
 232  
 233    read_reg : process (CLK)
 234    begin
 235      if (CLK'event) and (CLK = '1') then
 236          -- when input data not written
 237        if (sample_req = '1') then
 238           sample_out <= bram_out;
 239        end if;
 240      end if;
 241    end process;
 242  
 243    -- read from BRAM and send data
 244    addr_rd_cntr : process (RST, CLK)
 245    begin
 246      if (RST = '1') then
 247         rd_cntr <= "000000001";
 248      elsif (CLK'event) and (CLK = '1') then
 249         if (sample_req = '1') then
 250           if (EN = '1') then
 251             rd_cntr <= rd_cntr + 1;
 252           end if;
 253         end if;
 254      end if;
 255    end process;
 256  
 257    ADDR_RD <= rd_cntr;
 258  
 259  end architecture basic;
 260