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aic23b_dsp_read.vhd

   1  -- top.vhd: Digital Audio Codec Receiving Interface in DSP Communication Mode
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Karel Slany <slany AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  use work.math_pack.all;
  49  
  50  -- digital audio receiving unit
  51  -- the audio codec has to be configured to operate in DSP master mode
  52  entity aic23b_dsp_read is
  53    generic (
  54      DATA_WIDTH : integer := 16
  55    );
  56    port (
  57      -- Control signals
  58      CLK : in std_logic;
  59      RST : in std_logic;
  60  
  61      -- DATA interface
  62      LOUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
  63      ROUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
  64      DATA_VALID : out std_logic;
  65  
  66      -- CODEC interface
  67      ALRCOUT : in std_logic;
  68      ABCLK : in std_logic;
  69      ADOUT : in std_logic
  70    );
  71  end entity aic23b_dsp_read;
  72  
  73  architecture basic of aic23b_dsp_read is
  74  
  75    -- ABCLK rising edge detector and sampler
  76    signal abclk_re : std_logic;
  77    signal abclk_last : std_logic_vector(1 downto 0);
  78    signal alrcout_last : std_logic;
  79    signal adout_last : std_logic;
  80  
  81    -- sampled data from deserializer
  82    signal data : std_logic_vector(DATA_WIDTH-1 downto 0);
  83  
  84    -- sample bit counter
  85    signal start_cntr : std_logic;
  86    signal bit_cntr : std_logic_vector(log2(DATA_WIDTH)-1 downto 0);
  87    signal bit_cntr_load : std_logic;
  88  
  89    -- output finite state machine
  90    type FSMstate is (SInit, SReadL, SWriteL, SReadR, SWriteR, SWriteRReadL);
  91    signal pstate : FSMstate; -- actual state
  92    signal nstate : FSMstate; -- next state
  93    signal lwrite : std_logic;
  94    signal rwrite : std_logic;
  95  
  96  begin
  97  
  98    -- ABCLK rising edge detector and sampler
  99    abclk_re <= '1' when (abclk_last(1) = '0') and (abclk_last(0) = '1') else '0';
 100    abclk_detect_p : process (RST, CLK, ABCLK, ALRCOUT, ADOUT)
 101    begin
 102      if (RST = '1') then
 103        abclk_last <= ABCLK & ABCLK;
 104        alrcout_last <= ALRCOUT;
 105        adout_last <= ADOUT;
 106      elsif (CLK'event) and (CLK = '1') then
 107        abclk_last <= abclk_last(0) & ABCLK;
 108        alrcout_last <= ALRCOUT;
 109        adout_last <= ADOUT;
 110      end if;
 111    end process abclk_detect_p;
 112  
 113    -- deserializer
 114    deserializer_p : process (CLK)
 115    begin
 116      if (CLK'event) and (CLK='1') then
 117        if (abclk_re='1') then
 118          data <= data(DATA_WIDTH-2 downto 0) & adout_last;
 119        end if;
 120      end if;
 121    end process deserializer_p;
 122  
 123    -- bit counter process
 124    start_cntr <= '1' when (abclk_re = '1') and (alrcout_last = '1') else '0';
 125    bit_cntr_load <= '1' when (bit_cntr = conv_std_logic_vector(DATA_WIDTH-1, log2(DATA_WIDTH))) else '0';
 126    bit_cntr_p : process (RST, CLK)
 127    begin
 128      if (RST = '1') then
 129        bit_cntr <= (others => '0');
 130      elsif (CLK'event) and (CLK = '1') then
 131        -- synchronous reset
 132        if (start_cntr = '1') then
 133          bit_cntr <= (others => '0');
 134        -- increase counter when sample ready
 135        -- abclk_re must be tested, signals may last several
 136        -- CLK but only one abclk_re
 137        elsif (abclk_re = '1') then
 138          if (bit_cntr_load = '1') then
 139            bit_cntr <= (others => '0');
 140          else
 141            bit_cntr <= bit_cntr + 1;
 142          end if;
 143        end if;
 144      end if;
 145    end process bit_cntr_p;
 146  
 147    -- present state process
 148    pstate_p : process (RST, CLK)
 149    begin
 150      if (RST = '1') then
 151        pstate <= SInit;
 152      elsif (CLK'event) and (CLK = '1') then
 153        pstate <= nstate;
 154      end if;
 155    end process pstate_p;
 156  
 157    -- next state logic, output driving
 158    nstate_p : process (pstate, start_cntr, abclk_re, bit_cntr_load)
 159    begin
 160      -- default values
 161      nstate <= SInit;
 162      lwrite <= '0';
 163      rwrite <= '0';
 164  
 165      case pstate is
 166  
 167        when Sinit =>
 168          if (start_cntr = '1') then
 169            nstate <= SReadL;
 170          end if;
 171  
 172        when SReadL =>
 173          if (start_cntr = '1') then
 174            nstate <= SReadL;
 175          -- abclk_re must be tested, signals may last several
 176          -- CLK but only one abclk_re
 177          elsif (abclk_re = '1') and (bit_cntr_load = '1') then
 178            nstate <= SWriteL;
 179          else
 180            nstate <= SReadL;
 181          end if;
 182  
 183        when SWriteL =>
 184          lwrite <= '1';
 185          if (start_cntr = '1') then
 186            nstate <= SReadL;
 187          else
 188            nstate <= SReadR;
 189          end if;
 190  
 191        when SReadR =>
 192          -- abclk_re must be tested, signals may last several
 193          -- CLK but only one abclk_re
 194          if (abclk_re = '1') and (bit_cntr_load = '1') then
 195            if (start_cntr = '1') then
 196              -- last sample arrived during next window anouncement
 197              nstate <= SWriteRReadL;
 198            else
 199              nstate <= SWriteR;
 200            end if;
 201          elsif (start_cntr = '1') then
 202            nstate <= SReadL;
 203          else
 204            nstate <= SReadR;
 205          end if;
 206  
 207        when SWriteR =>
 208          rwrite <= '1';
 209          if (start_cntr = '1') then
 210            nstate <= SReadL;
 211          else
 212            nstate <= SInit;
 213          end if;
 214  
 215        when SWriteRReadL =>
 216          rwrite <= '1';
 217          if (start_cntr = '1') then
 218            nstate <= SReadL;
 219          else
 220            nstate <= SReadL;
 221          end if;
 222  
 223        when others => null;
 224  
 225      end case;
 226    end process nstate_p;
 227  
 228    -- output registers
 229    output_p : process (RST, CLK)
 230    begin
 231      if (RST = '1') then
 232        LOUT <= (others => '0');
 233        ROUT <= (others => '0');
 234        DATA_VALID <= '0';
 235      elsif (CLK'event) and (CLK = '1') then
 236        DATA_VALID <= '0';
 237        if (lwrite = '1') then
 238          LOUT <= data;
 239        end if;
 240        if (rwrite = '1') then
 241          DATA_VALID <= '1';
 242          ROUT <= data;
 243        end if;
 244      end if;
 245    end process output_p;
 246  
 247  end architecture basic;
 248  
Zobrazeno: 595861x Naposledy: 22.1.2022 10:14:53