SVN Repository / Prohlížení

tetris_top.vhd

   1  -- IMP project, Izidor Matusov, xmatus19, source: snake_top.vhd, changes cca 12%
   2  -- Increased colors to 16, changed VRAM component
   3  --
   4  -- tetris_top.vhd : VGA - 64x64 block graphics with pallete of 16 colors
   5  -- Copyright (C) 2008, 2010 Brno University of Technology,
   6  --                          Faculty of Information Technology
   7  -- Author(s): Izidor Matusov <xmatus19 AT stud.fit.vutbr.cz>
   8  --            Zdenek Vasicek <vasicek AT fit.vutbr.cz>
   9  --            Karel Slany    <slany AT fit.vutbr.cz>
  10  --
  11  -- LICENSE TERMS
  12  --
  13  -- Redistribution and use in source and binary forms, with or without
  14  -- modification, are permitted provided that the following conditions
  15  -- are met:
  16  -- 1. Redistributions of source code must retain the above copyright
  17  --    notice, this list of conditions and the following disclaimer.
  18  -- 2. Redistributions in binary form must reproduce the above copyright
  19  --    notice, this list of conditions and the following disclaimer in
  20  --    the documentation and/or other materials provided with the
  21  --    distribution.
  22  -- 3. All advertising materials mentioning features or use of this software
  23  --    or firmware must display the following acknowledgement:
  24  --
  25  --      This product includes software developed by the University of
  26  --      Technology, Faculty of Information Technology, Brno and its
  27  --      contributors.
  28  --
  29  -- 4. Neither the name of the Company nor the names of its contributors
  30  --    may be used to endorse or promote products derived from this
  31  --    software without specific prior written permission.
  32  --
  33  -- This software is provided ``as is'', and any express or implied
  34  -- warranties, including, but not limited to, the implied warranties of
  35  -- merchantability and fitness for a particular purpose are disclaimed.
  36  -- In no event shall the company or contributors be liable for any
  37  -- direct, indirect, incidental, special, exemplary, or consequential
  38  -- damages (including, but not limited to, procurement of substitute
  39  -- goods or services; loss of use, data, or profits; or business
  40  -- interruption) however caused and on any theory of liability, whether
  41  -- in contract, strict liability, or tort (including negligence or
  42  -- otherwise) arising in any way out of the use of this software, even
  43  -- if advised of the possibility of such damage.
  44  --
  45  -- $Id$
  46  --
  47  --
  48  library IEEE;
  49  use IEEE.std_logic_1164.ALL;
  50  use ieee.std_logic_arith.all;
  51  use ieee.std_logic_unsigned.all;
  52  use work.vga_controller_cfg.all;
  53  use work.clkgen_cfg.all;
  54  
  55  architecture arch_vga_mode of tlv_pc_ifc is
  56  
  57     signal irgb : std_logic_vector(8 downto 0);
  58     signal rrow : std_logic_vector(11 downto 0);
  59     signal rcol : std_logic_vector(11 downto 0);
  60     signal border: std_ulogic;
  61  
  62     -- Port A VIDEORAM
  63     signal spi_vram_addr    : std_logic_vector (11 downto 0);
  64     signal spi_vram_data_out: std_logic_vector (7 downto 0);
  65     signal spi_vram_data_in : std_logic_vector (7 downto 0);
  66     signal spi_vram_data_in0 : std_logic_vector (7 downto 0);
  67     signal spi_vram_data_in1 : std_logic_vector (7 downto 0);
  68     signal spi_vram_write_en: std_logic;
  69     signal spi_vram_read_en : std_logic;
  70     signal vram0_en : std_logic;
  71     signal vram1_en : std_logic;
  72  
  73     -- Port B VGARAM
  74     signal vga_bram_addr    : std_logic_vector (11 downto 0);
  75     signal vga_bram_dout    : std_logic_vector (3 downto 0);
  76  
  77     signal vga_mode  : std_logic_vector(60 downto 0); -- default 640x480x60
  78  
  79     -- Keyboard is controlled by MCU
  80     signal spi_kbrd_data_out : std_logic_vector(15 downto 0);
  81     signal spi_kbrd_data_in  : std_logic_vector(15 downto 0);
  82     signal spi_kbrd_we       : std_logic;
  83  
  84     -- display
  85     signal dis_addr     : std_logic_vector(0 downto 0);
  86     signal dis_data_out : std_logic_vector(15 downto 0);
  87     signal dis_write_en : std_logic;
  88  
  89     -- SPI interface
  90     component SPI_adc
  91        generic (
  92           ADDR_WIDTH : integer;
  93           DATA_WIDTH : integer;
  94           ADDR_OUT_WIDTH : integer;
  95           BASE_ADDR  : integer;
  96           DELAY : integer := 0
  97        );
  98        port (
  99           CLK      : in  std_logic;
 100  
 101           CS       : in  std_logic;
 102           DO       : in  std_logic;
 103           DO_VLD   : in  std_logic;
 104           DI       : out std_logic;
 105           DI_REQ   : in  std_logic;
 106  
 107           ADDR     : out  std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
 108           DATA_OUT : out  std_logic_vector (DATA_WIDTH-1 downto 0);
 109           DATA_IN  : in   std_logic_vector (DATA_WIDTH-1 downto 0);
 110  
 111           WRITE_EN : out  std_logic;
 112           READ_EN  : out  std_logic
 113        );
 114     end component;
 115  
 116     component RAMB16_S4_S4
 117        port (
 118           DOA   : out std_logic_vector(3 downto 0);
 119           ADDRA : in std_logic_vector(11 downto 0);
 120           CLKA  : in std_ulogic;
 121           DIA   : in std_logic_vector(3 downto 0);
 122           ENA   : in std_ulogic;
 123           SSRA  : in std_ulogic;
 124           WEA   : in std_ulogic;
 125  
 126           DOB   : out std_logic_vector(3 downto 0);
 127           ADDRB : in std_logic_vector(11 downto 0);
 128           CLKB  : in std_ulogic;
 129           DIB   : in std_logic_vector(3 downto 0);
 130           ENB   : in std_ulogic;
 131           SSRB  : in std_ulogic;
 132           WEB   : in std_ulogic
 133        );
 134     end component;
 135  
 136     -- Keyboard 4x4
 137     component keyboard_controller
 138        port(
 139           CLK      : in std_logic;
 140           RST      : in std_logic;
 141  
 142           DATA_OUT : out std_logic_vector(15 downto 0);
 143           DATA_VLD : out std_logic;
 144  
 145           KB_KIN   : out std_logic_vector(3 downto 0);
 146           KB_KOUT  : in  std_logic_vector(3 downto 0)
 147        );
 148     end component;
 149  
 150     component lcd_raw_controller
 151        port (
 152           RST      : in std_logic;
 153           CLK      : in std_logic;
 154  
 155           DATA_IN  : in std_logic_vector (15 downto 0);
 156           WRITE_EN : in std_logic;
 157  
 158           DISPLAY_RS   : out   std_logic;
 159           DISPLAY_DATA : inout std_logic_vector(7 downto 0);
 160           DISPLAY_RW   : out   std_logic;
 161           DISPLAY_EN   : out   std_logic
 162        );
 163     end component;
 164  
 165  begin
 166     -- Set graphical mode (640x480, 60 Hz refresh)
 167     setmode(r640x480x60, vga_mode);
 168  
 169     -- spi decoder (videoRAM)
 170     SPI_adc_ram: SPI_adc
 171        generic map(
 172           ADDR_WIDTH => 16,
 173           DATA_WIDTH => 8,
 174           ADDR_OUT_WIDTH => 12,
 175           BASE_ADDR  => 16#8000#, -- memory address range is 0x8000 - 0x9FFF
 176           DELAY => 1
 177        )
 178        port map(
 179           CLK      => CLK,
 180           CS       => SPI_CS,
 181  
 182           DO       => SPI_DO,
 183           DO_VLD   => SPI_DO_VLD,
 184           DI       => SPI_DI,
 185           DI_REQ   => SPI_DI_REQ,
 186  
 187           ADDR     => spi_vram_addr,
 188           DATA_OUT => spi_vram_data_out,
 189           DATA_IN  => spi_vram_data_in,
 190           WRITE_EN => spi_vram_write_en,
 191           READ_EN  => open
 192        );
 193  
 194     spi_vram_data_out(7 downto 4) <= (others => '0');
 195  
 196     blkram_vram0: RAMB16_S4_S4
 197        port map (
 198           DOA             => spi_vram_data_in(3 downto 0),
 199           ADDRA           => spi_vram_addr,
 200           CLKA            => CLK,
 201           DIA             => spi_vram_data_out(3 downto 0),
 202           ENA             => '1',
 203           SSRA            => '0',
 204           WEA             => spi_vram_write_en,
 205  
 206           DOB             => vga_bram_dout,
 207           ADDRB           => vga_bram_addr,
 208           CLKB            => CLK,
 209           DIB             => (others => '0'),
 210           ENB             => '1',
 211           SSRB            => '0',
 212           WEB             => '0'
 213        );
 214  
 215     -- spi decoder - keyboard
 216     SPI_adc_kbrd: SPI_adc
 217        generic map(
 218           ADDR_WIDTH => 8,
 219           DATA_WIDTH => 16,
 220           ADDR_OUT_WIDTH => 1,
 221           BASE_ADDR  => 16#02#
 222        )
 223        port map(
 224           CLK      => CLK,
 225           CS       => SPI_CS,
 226  
 227           DO       => SPI_DO,
 228           DO_VLD   => SPI_DO_VLD,
 229           DI       => SPI_DI,
 230           DI_REQ   => SPI_DI_REQ,
 231  
 232           ADDR     => open,
 233           DATA_OUT => open,
 234           DATA_IN  => spi_kbrd_data_in,
 235           WRITE_EN => open,
 236           READ_EN  => open
 237        );
 238  
 239     -- Keyboard controller
 240     kbrd_ctrl: entity work.keyboard_controller(arch_keyboard)
 241        port map (
 242           CLK => SMCLK,
 243           RST => RESET,
 244  
 245           DATA_OUT => spi_kbrd_data_in(15 downto 0),
 246           DATA_VLD => open,
 247  
 248           KB_KIN   => KIN,
 249           KB_KOUT  => KOUT
 250        );
 251  
 252     -- SPI decoder for display
 253     spidecd: SPI_adc
 254           generic map (
 255              ADDR_WIDTH => 8,
 256              DATA_WIDTH => 16,
 257              ADDR_OUT_WIDTH => 1,
 258              BASE_ADDR  => 16#00#
 259           )
 260           port map (
 261              CLK      => CLK,
 262              CS       => SPI_CS,
 263  
 264              DO       => SPI_DO,
 265              DO_VLD   => SPI_DO_VLD,
 266              DI       => SPI_DI,
 267              DI_REQ   => SPI_DI_REQ,
 268  
 269              ADDR     => dis_addr,
 270              DATA_OUT => dis_data_out,
 271              DATA_IN  => "0000000000000000",
 272              WRITE_EN => dis_write_en,
 273              READ_EN  => open
 274           );
 275  
 276     -- LCD display controller
 277     lcdctrl: lcd_raw_controller
 278           port map (
 279              RST    =>  RESET,
 280              CLK    =>  CLK, -- 25MHz
 281  
 282              -- control singals
 283              DATA_IN  => dis_data_out,
 284              WRITE_EN => dis_write_en,
 285  
 286              --- display's signals
 287              DISPLAY_RS   => LRS,
 288              DISPLAY_DATA => LD,
 289              DISPLAY_RW   => LRW,
 290              DISPLAY_EN   => LE
 291           );
 292  
 293     -- VGA controller, delay 1 tact
 294     vga: entity work.vga_controller(arch_vga_controller)
 295        generic map (REQ_DELAY => 1)
 296        port map (
 297           CLK    => CLK,
 298           RST    => RESET,
 299           ENABLE => '1',
 300           MODE   => vga_mode,
 301  
 302           DATA_RED    => irgb(8 downto 6),
 303           DATA_GREEN  => irgb(5 downto 3),
 304           DATA_BLUE   => irgb(2 downto 0),
 305           ADDR_COLUMN => rcol,
 306           ADDR_ROW    => rrow,
 307  
 308           VGA_RED   => RED_V,
 309           VGA_BLUE  => BLUE_V,
 310           VGA_GREEN => GREEN_V,
 311           VGA_HSYNC => HSYNC_V,
 312           VGA_VSYNC => VSYNC_V
 313        );
 314  
 315     -- Convert request for VGA (row, column) into VideoRAM address
 316     vga_bram_addr <= rrow(8 downto 3) & rcol(8 downto 3);
 317  
 318  
 319     -- Choose color based on value returned from memory
 320     select_color: process(vga_bram_dout)
 321     begin
 322      if rrow(11 downto 9) /= "000" or rcol(11 downto 9) /= "000" or rcol(8 downto 0) = "000000000" then
 323          -- eliminate requests not within range 64x64 blocks
 324          irgb <= "000000000";
 325      else
 326          -- Decode color from palette
 327          case vga_bram_dout is
 328              -- Wall (white)
 329              when "0001" => irgb <= "111111111";
 330  
 331              -- Fallen blocks + drawings (gray)
 332              when "0010" => irgb <= "100100100";
 333  
 334              -- Random colors begin here
 335              when "0011" => irgb <= "111111000"; -- yellow
 336              when "0100" => irgb <= "000000111"; -- blue
 337              when "0101" => irgb <= "110100111"; -- light magenta
 338              when "0110" => irgb <= "000100010"; -- dark green
 339              when "0111" => irgb <= "100111000"; -- light green
 340              when "1000" => irgb <= "100111111"; -- light cyan
 341              when "1001" => irgb <= "000111000"; -- green
 342              when "1010" => irgb <= "000100111"; -- light blue
 343              when "1011" => irgb <= "111001000"; -- light red
 344              when "1100" => irgb <= "110100011"; -- light brown
 345              when "1101" => irgb <= "111000000"; -- red
 346              when "1110" => irgb <= "100001110"; -- magenta
 347              when "1111" => irgb <= "000011101"; -- cyan
 348  
 349              -- Otherwise black colors
 350              when others =>
 351                 irgb <= "000000000";
 352          end case;
 353      end if;
 354     end process;
 355  
 356  end arch_vga_mode;
 357