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Aktuální adresář: FITkit / trunk / apps / games / pexeso / fpga /

tb_random.vhd

   1  LIBRARY ieee;
   2  USE ieee.std_logic_1164.ALL;
   3  
   4  ENTITY testbench IS
   5  END testbench;
   6  
   7  ARCHITECTURE behavior OF testbench IS
   8     --Input and Output definitions.
   9     signal clk : std_logic := '0';
  10     signal random_num : std_logic_vector(3 downto 0);
  11     -- Clock period definitions
  12     constant clk_period : time := 1 ns;
  13  BEGIN
  14          -- Instantiate the Unit Under Test (UUT)
  15     uut: entity work.random generic map (width => 4) PORT MAP (
  16            clk => clk,
  17            random_num => random_num
  18          );
  19     -- Clock process definitions
  20     clk_process :process
  21     begin
  22                  clk <= '0';
  23                  wait for clk_period/2;
  24                  clk <= '1';
  25                  wait for clk_period/2;
  26     end process;
  27  
  28  END;
Zobrazeno: 665622x Naposledy: 23.5.2022 01:27:16