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symbol_ram.vhd

   1  -- Pexeso - simple pure FPGA game
   2  -- Author: Vojtech Mrazek (xmraze06)
   3  
   4  library IEEE;
   5  use IEEE.std_logic_1164.ALL;
   6  use ieee.std_logic_arith.all;
   7  use ieee.std_logic_unsigned.all;
   8  use work.vga_controller_cfg.all;
   9  use work.clkgen_cfg.all;
  10  
  11  entity symbol_ram is
  12     generic (
  13        ADDRESS_SIZE : integer := 4;
  14        SYMBOL_SIZE  : integer := 4
  15     );
  16     port (
  17        CLK : in std_logic;
  18        RESET : in std_logic;
  19        GEN : in std_logic;
  20  
  21        -- Port pro CTL
  22        ADDR_A : in std_logic_vector(ADDRESS_SIZE - 1 downto 0);
  23        DATA_A : out std_logic_vector(SYMBOL_SIZE - 1 downto 0);
  24  
  25  
  26        -- Port pro zapis
  27        ADDR_W : in std_logic_vector(ADDRESS_SIZE - 1 downto 0);
  28        DATA_W : in std_logic_vector(SYMBOL_SIZE - 1 downto 0);
  29        WE     : in std_logic;
  30  
  31        -- Port pro VGA
  32        ADDR_B : in std_logic_vector(ADDRESS_SIZE - 1 downto 0);
  33        DATA_B : out std_logic_vector(SYMBOL_SIZE - 1 downto 0)
  34  
  35     );
  36  end symbol_ram;
  37  
  38  architecture behv of symbol_ram is
  39     type t_mem is array(2**ADDRESS_SIZE-1 downto 0) of std_logic_vector(SYMBOL_SIZE - 1 downto 0);
  40     signal symbols : t_mem := ("0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111","1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111");
  41  
  42     signal random : std_logic_vector(3 downto 0);
  43  
  44  begin
  45     rand: entity work.random
  46        generic map (width => 4)
  47        port map (
  48           clk => CLK,
  49           random_num => random
  50        );
  51  
  52     write: process
  53        variable in_set : std_logic := '0';
  54        variable element : std_logic_vector(3 downto 0);
  55        variable addr : std_logic_vector(3 downto 0);
  56  
  57     begin
  58        if CLK'event and CLK='1' then
  59           if RESET = '1' or GEN='1' then
  60              for I in 0 to 15 loop
  61                 symbols(I) <= "0000";
  62              end loop;
  63  
  64              if GEN='1' then
  65                 in_set := '1';
  66                 element := "0000";
  67                 addr := random;
  68              end if;
  69  
  70           -- zkusim nastavit
  71           elsif in_set='1' then
  72              if symbols(conv_integer(addr))(3) = '0' then
  73                 symbols(conv_integer(addr)) <= "1" & element(2 downto 0);
  74                 element := element + 1;
  75                 addr := random;
  76                 if element = "0000" then
  77                    in_set := '0';
  78                 end if;
  79              else
  80                 addr := addr + 1;
  81              end if;
  82  
  83           elsif WE='1' then
  84              symbols(conv_integer(ADDR_W)) <= DATA_W;
  85           end if;
  86        end if;
  87     end process;
  88  
  89     read: process
  90     begin
  91        if CLK'event and CLK='1' then
  92           DATA_A <= symbols(conv_integer(ADDR_A));
  93           DATA_B <= symbols(conv_integer(ADDR_B));
  94        end if;
  95     end process;
  96  
  97  end;