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Aktuální adresář: FITkit / trunk / apps / games / pexeso / fpga /

random.vhd

   1  -- Random number generator
   2  library IEEE;
   3  use IEEE.STD_LOGIC_1164.ALL;
   4  
   5  entity random is
   6     generic ( width : integer :=  4 );
   7     port (
   8        clk : in std_logic;
   9        random_num : out std_logic_vector (width-1 downto 0)   --output vector
  10     );
  11  end random;
  12  
  13  architecture Behavioral of random is
  14     begin
  15        process(clk)
  16           variable rand_temp : std_logic_vector(width+5 downto 0) := (5 => '1',others => '0');
  17           variable temp : std_logic := '0';
  18        begin
  19           if(rising_edge(clk)) then
  20              temp := rand_temp(width+5) xor rand_temp(width+4);
  21              rand_temp(width+5 downto 1) := rand_temp(width+4 downto 0);
  22              rand_temp(0) := temp;
  23           end if;
  24           -- Posun o 1 bit, jinak by tam nebyla nikdy 0000
  25           random_num <= rand_temp(width+5 downto 5);
  26        end process;
  27  end;
Zobrazeno: 665642x Naposledy: 23.5.2022 02:00:01