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Aktuální adresář: FITkit / trunk / apps / games / pexeso / fpga /

pexeso_top.vhd

   1  -- pexeso_top.vhd : Pexeso - simple FPGA game
   2  -- Copyright (C) 2011 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Vojtech Mrazek <xmraze06 AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.std_logic_1164.ALL;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  use work.vga_controller_cfg.all;
  49  use work.clkgen_cfg.all;
  50  
  51  architecture behav of tlv_pc_ifc is
  52  
  53     -- VGA signals
  54     signal vga_mode   : std_logic_vector(60 downto 0); -- default 640x480x60
  55     signal vga_row    : std_logic_vector(11 downto 0);
  56     signal vga_col    : std_logic_vector(11 downto 0);
  57  
  58     signal vga_rgb    : std_logic_vector(8 downto 0);
  59  
  60     signal sym_color  : std_logic_vector(3 downto 0);
  61  
  62     signal sym_rd_addr : std_logic_vector(3 downto 0);
  63     signal sym_rd_data : std_logic_vector(3 downto 0);
  64     signal sym_wr_addr : std_logic_vector(3 downto 0);
  65     signal sym_wr_data : std_logic_vector(3 downto 0);
  66     signal sym_we      : std_logic;
  67     signal sym_gen     : std_logic;
  68  
  69     signal sym_vga_sym : std_logic_vector(3 downto 0);
  70     signal sym_vga_addr : std_logic_vector(3 downto 0);
  71  
  72     -- cursor signals
  73     signal cur_x   : std_logic_vector(1 downto 0) := "00";
  74     signal cur_y   : std_logic_vector(1 downto 0) := "00";
  75  
  76     signal kbrd_data_out : std_logic_vector(15 downto 0);
  77     signal kbrd_data_vld : std_logic;
  78  
  79     signal ctl_enter, ctl_reset : std_logic;
  80  
  81     -- character decoder
  82     signal char_symbol : std_logic_vector(3 downto 0) := "1010";
  83     signal char_data : std_logic;
  84  
  85     -- bcd counter
  86     signal bcd_clk, bcd_reset : std_logic;
  87     signal bcd_data0, bcd_data1 : std_logic_vector(3 downto 0);
  88  begin
  89     -- ----------------------------------------------------------
  90     -- ------------- GLOBAL MODULES -----------------------------
  91     -- ----------------------------------------------------------
  92  
  93     -- VGA controller, delay 1 tact
  94     vga: entity work.vga_controller(arch_vga_controller)
  95        generic map (REQ_DELAY => 1)
  96        port map (
  97           CLK    => CLK,
  98           RST    => RESET,
  99           ENABLE => '1',
 100           MODE   => vga_mode,
 101  
 102           DATA_RED    => vga_rgb(8 downto 6) ,
 103           DATA_GREEN  => vga_rgb(5 downto 3),
 104           DATA_BLUE   => vga_rgb(2 downto 0),
 105           ADDR_COLUMN => vga_col,
 106           ADDR_ROW    => vga_row,
 107  
 108           VGA_RED   => RED_V,
 109           VGA_BLUE  => BLUE_V,
 110           VGA_GREEN => GREEN_V,
 111           VGA_HSYNC => HSYNC_V,
 112           VGA_VSYNC => VSYNC_V
 113        );
 114     -- Set graphical mode (640x480, 60 Hz refresh)
 115     setmode(r640x480x60, vga_mode);
 116  
 117     -- char 2 vga decoder
 118     chardec : entity work.char_rom
 119        port map (
 120           ADDRESS => char_symbol,
 121           ROW => vga_row(3 downto 0),
 122           COLUMN => vga_col(2 downto 0),
 123           DATA => char_data
 124        );
 125  
 126     sym: entity work.symbol_decoder
 127        port map (
 128           CLK => CLK,
 129           SYMBOL => sym_vga_sym,
 130  
 131           ROW => vga_row(5 downto 1),
 132           COL => vga_col(5 downto 1),
 133  
 134           COLOR => sym_color
 135        );
 136  
 137     symram: entity work.symbol_ram
 138        generic map (
 139           ADDRESS_SIZE => 4,
 140           SYMBOL_SIZE  => 4
 141        )
 142        port map (
 143           CLK => CLK,
 144           RESET => RESET,
 145           GEN => sym_gen,
 146  
 147           -- Port pro CTL
 148           ADDR_A => sym_rd_addr,
 149           DATA_A => sym_rd_data,
 150  
 151  
 152           -- Port pro zapis
 153           ADDR_W => sym_wr_addr,
 154           DATA_W => sym_wr_data,
 155           WE     => sym_we,
 156  
 157           -- Port pro VGA
 158           ADDR_B => sym_vga_addr,
 159           DATA_B => sym_vga_sym
 160  
 161        );
 162  
 163     -- Keyboard controller
 164     kbrd_ctrl: entity work.keyboard_controller(arch_keyboard)
 165        port map (
 166           CLK => SMCLK,
 167           RST => RESET,
 168  
 169           DATA_OUT => kbrd_data_out(15 downto 0),
 170           DATA_VLD => kbrd_data_vld,
 171  
 172           KB_KIN   => KIN,
 173           KB_KOUT  => KOUT
 174        );
 175  
 176     -- BCD counter
 177     bcd_cnt: entity work.bcd_cnt
 178        port map (
 179           CLK => bcd_clk,
 180           RESET => bcd_reset,
 181  
 182           DATA0 => bcd_data0,
 183           DATA1 => bcd_data1
 184        );
 185  
 186     -- FSM for game
 187     game_fsm : entity work.game_ctl
 188        port map (
 189           CLK => CLK,
 190           RESET => RESET,
 191  
 192           -- cursor
 193           CUR_X => cur_x,
 194           CUR_Y => cur_y,
 195  
 196           ENTER   => ctl_enter,
 197           RESTART => ctl_reset,
 198  
 199           RAM_GEN => sym_gen,
 200           CNT_CLK => bcd_clk,
 201           CNT_RST => bcd_reset,
 202  
 203           -- Port pro CTL
 204           RAM_ADDR_A => sym_rd_addr,
 205           RAM_DATA_A => sym_rd_data,
 206  
 207  
 208           -- Port pro zapis
 209           RAM_ADDR_W => sym_wr_addr,
 210           RAM_DATA_W => sym_wr_data,
 211           RAM_WE     => sym_we
 212  
 213        );
 214  
 215     -- cursor controller, move to CLK
 216     cursor: process
 217        variable in_access : std_logic := '0';
 218     begin
 219        if CLK'event and CLK='1' then
 220           ctl_enter <= '0';
 221           ctl_reset <= '0';
 222  
 223           if in_access='0' then
 224              if kbrd_data_vld='1' then
 225                 in_access:='1';
 226                 if kbrd_data_out(9)='1' and cur_x /= "11" then  -- key 6
 227                    cur_x <= cur_x+1;
 228                 elsif kbrd_data_out(1)='1' and cur_x /= "00" then  -- key 4
 229                    cur_x <= cur_x-1;
 230                 elsif kbrd_data_out(4)='1' and cur_y /= "00" then  -- key 2
 231                    cur_y <= cur_y-1;
 232                 elsif kbrd_data_out(6)='1' and cur_y /= "11" then  -- key 8
 233                    cur_y <= cur_y+1;
 234                 elsif kbrd_data_out(5)='1' then     -- key 5
 235                    ctl_enter <= '1';
 236  
 237                 elsif kbrd_data_out(12)='1' then    -- key A
 238                    ctl_reset <= '1';
 239  
 240  
 241                 end if;
 242              end if;
 243           else
 244              if kbrd_data_vld='0' then
 245                 in_access:='0';
 246              end if;
 247           end if;
 248        end if;
 249  
 250     end process;
 251  
 252  
 253  
 254     setgraph : process (vga_row, vga_col)
 255        variable in_row : std_logic := '0';
 256        variable in_col : std_logic := '0';
 257        variable in_nmr_row, in_sym_1, in_sym_2 : std_logic;
 258  
 259        variable col_id : std_logic_vector(3 downto 0);
 260     begin
 261        if CLK'event and CLK='1' then
 262           vga_rgb <= "000000000";    -- default color
 263           if in_sym_1 = '1' then
 264              char_symbol <= bcd_data1;
 265           else
 266              char_symbol <= bcd_data0;
 267           end if;
 268  
 269           if vga_row=0 or vga_row=386 then
 270              in_row :='0';
 271           elsif vga_row=128 then
 272              in_row :='1';
 273           end if;
 274  
 275           if vga_col=0 or vga_col=450 then
 276              in_col :='0';
 277           elsif vga_col=192 then
 278              in_col :='1';
 279           end if;
 280  
 281           if vga_col=0 or vga_col=447 then
 282              in_sym_1 := '0';
 283              in_sym_2 := '0';
 284           elsif vga_col=431 then
 285              in_sym_1 := '1';
 286           elsif vga_col=439 then
 287              in_sym_1 := '0';
 288              in_sym_2 := '1';
 289           end if;
 290  
 291           if vga_row=0 or vga_row=416 then
 292              in_nmr_row:='0';
 293           elsif vga_row=400 then
 294              in_nmr_row:='1';
 295           end if;
 296  
 297           col_id := vga_col(9 downto 6) - 3;
 298           sym_vga_addr <= not vga_row(7) & vga_row(6) & col_id(1 downto 0);
 299  
 300  
 301           if in_row = '1' and in_col = '1' then
 302              if vga_row(5 downto 1)="00000" or vga_col(5 downto 1)="00000" then
 303                    vga_rgb <= "100100100";
 304              else
 305                 -- GRID
 306                 if  not vga_row(7) & vga_row(6) & col_id(1 downto 0) =cur_y & cur_x and vga_row(1)='1' and vga_col(1)='1' then
 307                    vga_rgb <= "111000000";
 308                 else
 309                    -- CARD
 310              		case sym_color is
 311              			when "0000" => vga_rgb <= "000000000"; -- black
 312              		   when "0001" => vga_rgb <= "000000111"; -- blue
 313                       when "0010" => vga_rgb <= "100100100"; -- gray
 314                       when "0011" => vga_rgb <= "111111000"; -- yellow
 315                       when "0100" => vga_rgb <= "111000000"; -- red
 316                       when "0101" => vga_rgb <= "110100111"; -- light magenta
 317                       when "0110" => vga_rgb <= "000100010"; -- dark green
 318                       when "0111" => vga_rgb <= "100111000"; -- light green
 319                       when "1000" => vga_rgb <= "100001110"; -- magenta
 320                       when "1010" => vga_rgb <= "000100111"; -- light blue
 321              			when others => vga_rgb <= "111111111"; -- white
 322              		end case;
 323           		end if;
 324           	end if;
 325           elsif in_nmr_row='1' and (in_sym_1 = '1' or in_sym_2 = '1') then
 326              if char_data = '1' then
 327                 vga_rgb <= "111111111"; -- white
 328              end if;
 329           end if;
 330  		end if;
 331     end process;
 332  
 333  
 334     X(13) <= '1';
 335     X(15) <= '0';
 336  
 337  
 338  end behav;
 339  
Zobrazeno: 665644x Naposledy: 23.5.2022 02:02:49