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game_ctl.vhd

   1  -- Pexeso - simple pure FPGA game
   2  -- Author: Vojtech Mrazek (xmraze06)
   3  
   4  library IEEE;
   5  use IEEE.std_logic_1164.ALL;
   6  use ieee.std_logic_arith.all;
   7  use ieee.std_logic_unsigned.all;
   8  use work.vga_controller_cfg.all;
   9  use work.clkgen_cfg.all;
  10  
  11  entity game_ctl is
  12     port (
  13        CLK : in std_logic;
  14        RESET : in std_logic;
  15  
  16        -- cursor
  17        CUR_X : in std_logic_vector(1 downto 0);
  18        CUR_Y : in std_logic_vector(1 downto 0);
  19  
  20  
  21        ENTER   : in std_logic;    --
  22        RESTART : in std_logic;
  23  
  24        RAM_GEN : out std_logic;    -- generovat novou sadu
  25  
  26  
  27  
  28        -- Port pro CTL
  29        RAM_ADDR_A : out std_logic_vector(3 downto 0);
  30        RAM_DATA_A : in std_logic_vector(3 downto 0);
  31  
  32  
  33        -- Port pro zapis
  34        RAM_ADDR_W : out std_logic_vector(3 downto 0);
  35        RAM_DATA_W : out std_logic_vector(3 downto 0);
  36        RAM_WE     : out std_logic
  37  
  38     );
  39  end game_ctl;
  40  
  41  architecture behv of game_ctl is
  42     type t_state is (INIT, WAITFIRST, WAITSECOND, WAITTIME, HIDEFIRST, HIDESECOND);
  43     signal pstate, nstate : t_state;
  44     signal card1, card2 : std_logic_vector(3 downto 0);
  45     signal card1data, card2data : std_logic_vector(2 downto 0);
  46  
  47     signal pairs : std_logic_vector(2 downto 0);
  48  
  49     signal clk_cntr : std_logic_vector(25 downto 0);
  50     signal clk_reset, clk_end : std_logic;
  51  begin
  52  
  53     process (CLK, RESET)
  54     begin
  55        if CLK'event and CLK='1' then
  56           if RESET='1' or RESTART = '1' then
  57              pstate <= INIT;
  58           else
  59              pstate <= nstate;
  60           end if;
  61        end if;
  62     end process;
  63  
  64     timer : process (CLK)
  65     begin
  66        if clk_reset = '1' then
  67           clk_cntr <= (others => '0');
  68        elsif CLK'event and CLK='1' then
  69           clk_cntr <= clk_cntr + 1;
  70        end if;
  71        clk_end <= clk_cntr(25);
  72     end process;
  73  
  74     nstate_logic : process (CLK)
  75     begin
  76        RAM_GEN <= '0';
  77        RAM_WE <= '0';
  78        RAM_ADDR_A <= CUR_Y & CUR_X;
  79        RAM_ADDR_W <= CUR_Y & CUR_X;
  80        clk_reset <= '0';
  81        RAM_DATA_W <= "0" & RAM_DATA_A(2 downto 0);
  82        CNT_CLK <= '0';
  83        CNT_RST <= '0';
  84  
  85        case pstate is
  86           -- Povoleni inicializace RAM
  87           when INIT =>
  88              RAM_GEN <= '1';
  89              nstate <= WAITFIRST;
  90              pairs <= "000";
  91              CNT_RST <= '1';
  92  
  93           -- Cekani na prvni kartu
  94           when WAITFIRST =>
  95              nstate <= WAITFIRST;
  96              if ENTER='1' then
  97                 if RAM_DATA_A(3) = '1' then
  98                    -- otoceni karty
  99                    RAM_DATA_W <= "0" & RAM_DATA_A(2 downto 0);
 100                    RAM_WE <= '1';
 101  
 102                    CNT_CLK <= '1';   -- zapocitej kartu
 103                    card1 <= CUR_Y & CUR_X;
 104                    card1data <= RAM_DATA_A(2 downto 0);
 105                    nstate <= WAITSECOND;
 106                 end if;
 107              end if;
 108  
 109           -- Cekani na druhou kartu
 110           when WAITSECOND =>
 111              nstate <= WAITSECOND;
 112              if ENTER='1' then
 113                 if RAM_DATA_A(3) = '1' and card1 /= CUR_Y & CUR_X  then
 114                    RAM_DATA_W <= "0" & RAM_DATA_A(2 downto 0);
 115                    RAM_WE <= '1';
 116                    card2 <= CUR_Y & CUR_X;
 117                    card2data <= RAM_DATA_A(2 downto 0);
 118                    if card1data = RAM_DATA_A(2 downto 0) then
 119                       nstate <= WAITFIRST;
 120                    else
 121                       nstate <= WAITTIME;
 122                       clk_reset <= '1';
 123                    end if;
 124                 end if;
 125              end if;
 126  
 127           -- Cekani na dobehnuti casovace
 128           when WAITTIME =>
 129              nstate <= WAITTIME;
 130              if clk_end = '1' then
 131                 if card1data = card2data then
 132                    nstate <= WAITFIRST;
 133                 else
 134                    nstate <= HIDEFIRST;
 135                 end if;
 136              end if;
 137  
 138           -- Skryti prvni karty
 139           when HIDEFIRST =>
 140              nstate <= HIDESECOND;
 141              RAM_ADDR_W <= card1;
 142              RAM_DATA_W <= "1" & card1data;
 143              RAM_WE <= '1';
 144  
 145           -- Skryti druhe karty
 146           when HIDESECOND =>
 147              nstate <= WAITFIRST;
 148              RAM_ADDR_W <= card2;
 149              RAM_DATA_W <= "1" & card2data;
 150              RAM_WE <= '1';
 151  
 152  
 153           when others =>
 154              nstate <= INIT;
 155  
 156        end case;
 157  
 158  
 159     end process;
 160  
 161  end;