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bcd_cnt.vhd

   1  -- Pexeso - simple pure FPGA game
   2  -- Author: Vojtech Mrazek (xmraze06)
   3  
   4  library IEEE;
   5  use IEEE.std_logic_1164.ALL;
   6  use ieee.std_logic_arith.all;
   7  use ieee.std_logic_unsigned.all;
   8  use work.vga_controller_cfg.all;
   9  use work.clkgen_cfg.all;
  10  
  11  entity bcd_cnt is
  12     port (
  13        CLK : in std_logic;
  14        RESET : in std_logic;
  15  
  16        DATA0 : out std_logic_vector(3 downto 0);
  17        DATA1 : out std_logic_vector(3 downto 0)
  18  
  19     );
  20  end bcd_cnt;
  21  
  22  architecture behv of bcd_cnt is
  23     signal sdata0,sdata1 : std_logic_vector(3 downto 0);
  24  begin
  25     process (CLK,RESET)
  26  
  27     begin
  28        if RESET='1' then
  29           sdata0 <= (others => '0');
  30           sdata1 <= (others => '0');
  31        elsif CLK'event and CLK='1' then
  32           if sdata0 = 9 then
  33              sdata0 <= "0000";
  34              if sdata1 = 9 then
  35                 sdata1 <= "0000";
  36              else
  37                 sdata1 <= sdata1 + 1;
  38              end if;
  39           else
  40              sdata0 <= sdata0 + 1;
  41           end if;
  42        end if;
  43  
  44     end process;
  45  
  46     DATA0 <= sdata0;
  47     DATA1 <= sdata1;
  48  
  49  end;