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top.vhd

   1  -- Top.vhd : keyboard
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek   vasicek@fit.vutbr.cz
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use ieee.std_logic_1164.ALL;
  46  use IEEE.numeric_std.all;
  47  use ieee.std_logic_ARITH.ALL;
  48  use ieee.std_logic_UNSIGNED.ALL;
  49  use work.clkgen_cfg.all;
  50  use work.serial_cfg.ALL;
  51  
  52  architecture main of tlv_bare_ifc is
  53  
  54     -- interrupt
  55     signal int_data_out  : std_logic_vector ( 7 downto 0);
  56     signal int_data_in   : std_logic_vector ( 7 downto 0);
  57     signal int_write_en  : std_logic;
  58     signal int_read_en   : std_logic;
  59     signal interrupt     : std_logic_vector ( 7 downto 0);
  60     signal interrupt_out : std_logic;
  61  
  62     --signaly pro komunikaci se seriovym rozhranim
  63     signal serial_data_out: std_logic_vector ( 7 downto 0);
  64     signal serial_data_in : std_logic_vector ( 7 downto 0);
  65     signal serial_write_en: std_logic;
  66     signal serial_read_en : std_logic;
  67     signal serial_vld     : std_logic;
  68     signal serial_busy    : std_logic;
  69  
  70     signal ser_data_out  : std_logic_vector ( 7 downto 0);
  71     signal ser_data_in   : std_logic_vector ( 7 downto 0);
  72     signal ser_write_en  : std_logic;
  73     signal ser_read_en   : std_logic;
  74  
  75     signal led   : std_logic := '1';
  76  
  77  begin
  78  
  79     -- SPI dekoder pro radic preruseni
  80     SPI_adc_INT: entity work.SPI_adc
  81        generic map(
  82           ADDR_WIDTH => 8,     -- sirka adresy 8 bitu
  83           DATA_WIDTH => 8,     -- sirka dat 8 bitu
  84           ADDR_OUT_WIDTH => 1, -- sirka adresy na vystupu min. 1 bit
  85           BASE_ADDR  => 16#80# -- adresovy prostor 0x0080
  86        )
  87        port map(
  88           CLK      => CLK,
  89  
  90           CS       => SPI_CS,
  91           DO       => SPI_DO,
  92           DO_VLD   => SPI_DO_VLD,
  93           DI       => SPI_DI,
  94           DI_REQ   => SPI_DI_REQ,
  95  
  96           ADDR     => open,
  97           DATA_OUT => int_data_out,
  98           DATA_IN  => int_data_in,
  99           WRITE_EN => int_write_en,
 100           READ_EN  => int_read_en
 101        );
 102  
 103     -- Radic preruseni
 104     IRQctrl: entity work.interrupt_controller
 105        port map(
 106           CLK    =>  CLK,
 107           RST    =>  RESET,
 108  
 109           IRQ_IN  => interrupt,
 110           IRQ_OUT => interrupt_out,   -- celkove vystupni preruseni
 111  
 112           -- vystupni vektor preruseni
 113           DATA_OUT    => int_data_in,
 114           READ_EN     => int_read_en,
 115  
 116           -- nastaveni masky preruseni
 117           DATA_IN     => int_data_out,
 118           WRITE_EN    => int_write_en
 119        );
 120  
 121     -- vystupni interrupt se nahodi jen pokud neprobiha prenos na sbernici SPI
 122     IRQ <= interrupt_out and not SPI_CS;
 123  
 124     -- nevyuzite zdroje preruseni uzemnime
 125     interrupt(7 downto 1) <= (others => '0');
 126     interrupt(0) <= serial_vld;
 127  
 128     -- SPI dekoder pro registr seriove linky
 129     SPI_adc_serial: entity work.SPI_adc
 130        generic map(
 131           ADDR_WIDTH => 8,     -- sirka adresy 8 bitu
 132           DATA_WIDTH => 8,     -- sirka dat 8 bitu
 133           ADDR_OUT_WIDTH => 1, -- sirka adresy na vystupu min. 1 bit
 134           BASE_ADDR  => 16#90#)
 135        port map(
 136           CLK      => CLK,
 137  
 138           CS       => SPI_CS,
 139           DO       => SPI_DO,
 140           DO_VLD   => SPI_DO_VLD,
 141           DI       => SPI_DI,
 142           DI_REQ   => SPI_DI_REQ,
 143  
 144           ADDR     => open,
 145           DATA_OUT => ser_data_out,
 146           WRITE_EN => ser_write_en,
 147  
 148           DATA_IN  => ser_data_in,
 149           READ_EN  => open
 150        );
 151  
 152     LEDF <= led;
 153  
 154     we_sync: entity work.clk_sync
 155        port map(
 156          RESET => RESET,
 157          CLK_FAST => CLK,
 158          CLK_SLOW => SMCLK,
 159  
 160          FAST_IN  => ser_write_en,
 161          SLOW_OUT => serial_write_en
 162        );
 163  
 164     dout_reg: process (CLK)
 165     begin
 166        if (CLK='1') and (CLK'event) then
 167           if (ser_write_en = '1') then
 168              led <= not led;
 169              serial_data_in <= ser_data_out;
 170           end if;
 171        end if;
 172     end process;
 173  
 174     din_reg: process (SMCLK)
 175     begin
 176        if (SMCLK='1') and (SMCLK'event) then
 177           if (serial_vld = '1') then
 178              ser_data_in <= serial_data_out;
 179           end if;
 180        end if;
 181     end process;
 182  
 183     -- radic seriove linky
 184     serial_tr: entity work.serial_transceiver
 185        generic map (
 186           SPEED     => s57600Bd,
 187           DATAWIDTH => 8,
 188           STOPBITS  => 1,
 189           PARITY    => sParityOdd
 190        )
 191        port map(
 192           RESET    => RESET,
 193           CLK      => SMCLK,
 194  
 195           -- cteni dat prijatych po seriove lince
 196           DATA_OUT => serial_data_out,
 197           DATA_VLD => serial_vld,
 198  
 199           -- pro vysilani dat na RS232
 200           DATA_IN  => serial_data_in,
 201           WRITE_EN => serial_write_en,
 202  
 203           BUSY     => serial_busy,
 204           ERR      => open,
 205           ERR_RST  => '0',
 206  
 207           RXD      => AFBUS(0),
 208           TXD      => AFBUS(1),
 209           RTS      => '0',
 210           CTS      => open
 211        );
 212  
 213  
 214  end main;
 215  
Zobrazeno: 715383x Naposledy: 4.10.2022 07:26:50