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clk_sync.vhd

   1  -- clk_sync.vhd: valid synchronization accross clock domains
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.STD_LOGIC_1164.ALL;
  46  
  47  entity clk_sync is
  48     port (
  49        RESET     : in std_logic;
  50        CLK_FAST  : in std_logic;
  51        CLK_SLOW  : in std_logic;
  52  
  53        FAST_IN  : in std_logic;
  54        SLOW_OUT : out std_logic
  55     );
  56  end clk_sync;
  57  
  58  
  59  architecture behavioral of clk_sync is
  60  
  61     signal val_rst : std_logic;
  62     signal val_set : std_logic;
  63  
  64  begin
  65  
  66     process (RESET, CLK_SLOW)
  67     begin
  68        if (RESET='1') then
  69           val_rst <= '0';
  70           SLOW_OUT <= '0';
  71        elsif (CLK_SLOW='1') and (CLK_SLOW'event) then
  72           val_rst <= '0';
  73           SLOW_OUT <= '0';
  74           if (val_set = '1') then
  75              SLOW_OUT <= '1';
  76              val_rst <= '1';
  77           end if;
  78        end if;
  79     end process;
  80  
  81     process (RESET, CLK_FAST)
  82     begin
  83        if (RESET='1') then
  84            val_set <= '0';
  85        elsif (CLK_FAST='1') and (CLK_FAST'event) then
  86            if (FAST_IN = '1') then
  87               val_set <= '1';
  88            elsif (val_rst = '1') then
  89               val_set <= '0';
  90            end if;
  91        end if;
  92     end process;
  93  
  94  end architecture;
  95  
  96  
Zobrazeno: 715387x Naposledy: 4.10.2022 08:04:25