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fspi.c

   1  /*******************************************************************************
   2     fspi.c: second SPI interface
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5     Author(s): Karel Slany <slany AT fit.vutbr.cz>
   6  
   7     LICENSE TERMS
   8  
   9     Redistribution and use in source and binary forms, with or without
  10     modification, are permitted provided that the following conditions
  11     are met:
  12     1. Redistributions of source code must retain the above copyright
  13        notice, this list of conditions and the following disclaimer.
  14     2. Redistributions in binary form must reproduce the above copyright
  15        notice, this list of conditions and the following disclaimer in
  16        the documentation and/or other materials provided with the
  17        distribution.
  18     3. All advertising materials mentioning features or use of this software
  19        or firmware must display the following acknowledgement:
  20  
  21          This product includes software developed by the University of
  22          Technology, Faculty of Information Technology, Brno and its
  23          contributors.
  24  
  25     4. Neither the name of the Company nor the names of its contributors
  26        may be used to endorse or promote products derived from this
  27        software without specific prior written permission.
  28  
  29     This software or firmware is provided ``as is'', and any express or implied
  30     warranties, including, but not limited to, the implied warranties of
  31     merchantability and fitness for a particular purpose are disclaimed.
  32     In no event shall the company or contributors be liable for any
  33     direct, indirect, incidental, special, exemplary, or consequential
  34     damages (including, but not limited to, procurement of substitute
  35     goods or services; loss of use, data, or profits; or business
  36     interruption) however caused and on any theory of liability, whether
  37     in contract, strict liability, or tort (including negligence or
  38     otherwise) arising in any way out of the use of this software, even
  39     if advised of the possibility of such damage.
  40  
  41     $Id$
  42  
  43  
  44  *******************************************************************************/
  45  
  46  #include "fspi.h"
  47  
  48  /**
  49   \brief SPI initialization
  50   **/
  51  void FSPI_Init(void)
  52  {
  53   #if defined MSP_16X
  54    /*
  55    // set SPI to UART0 (FITkit 1.x)
  56  
  57    U0CTL |= SWRST;                   /// reset SPI
  58    U0CTL = SWRST | CHAR | SYNC | MM; /// SPI mode, 8 bit, master mode
  59    U0TCTL = CKPL | SSEL_3 | STC;     /// SMCLK clock (7MHz), idle polarity 1
  60    U0BR0 = 2;                        /// max speed (SMCLK/2)
  61    U0BR1 = 0;
  62    ME2 |= USPIE1;                    /// enable SPI
  63  
  64    // I/O setup
  65    FSPI_PORT_DIR &= ~(FSPI_DI);         // inputs
  66    FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK; // outputs
  67    FSPI_PORT_OUT |= FSPI_DO | FSPI_CLK; // set outputs to 1
  68  
  69    FSPI_PORT_SEL |= FSPI_DI | FSPI_DO | FSPI_CLK; // connects pins to  USART
  70  
  71    U0CTL &= ~SWRST; // enable SPI (disable reset)
  72    */
  73   #elif defined MSP_261X
  74    // set SPI to UCB0 (FITkit 2.x)
  75  
  76    UCB0CTL1 = UCSWRST; /// reset UCB0
  77  
  78    UCB0CTL0 = UCCKPL | UCMST | UCMSB | UCMODE_0 | UCSYNC; /// SPI mode, 8 bit, master mode, idle polarity 1
  79    UCB0CTL1 |= UCSSEL_2;                                  /// SMCLK clock
  80    UCB0BR0 = 1;                                           /// speed SMCLK/1 = 14MHz
  81    UCB0BR1 = 0;
  82  
  83    // I/O setup
  84    FSPI_PORT_DIR &= ~(FSPI_DI);         // inputs
  85    FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK; // outputs
  86    FSPI_PORT_OUT |= FSPI_DO | FSPI_CLK; // set outputs to 1
  87  
  88    FSPI_PORT_SEL |= SPI_DI | SPI_DO | SPI_CLK; // connects pins to UCB0
  89  
  90    //UC1IFG = 0;
  91    UC0IE &= ~(UCB0TXIE | UCB0RXIE);
  92  
  93    UCB0CTL1 &= ~UCSWRST; // disable UCB0 reset
  94   #else
  95    #error "Can't initialize SPI"
  96   #endif
  97  }
  98  
  99  
 100  /**
 101   \brief Disables SPI
 102   **/
 103  void FSPI_Close(void)
 104  {
 105   #if defined MSP_16X
 106    /*
 107    // disable SPI
 108    ME2 &= ~USPIE1; // enable SPI
 109    U0CTL = SWRST;  // disable (reset) SPI
 110    */
 111   #elif defined MSP_261X
 112    UCB0CTL1 |= UCSWRST; /// reset UCB0
 113   #endif
 114  
 115    // disable I/O
 116    FSPI_PORT_SEL &= ~(FSPI_DI | FSPI_DO | FSPI_CLK);                // disconnect pins USART0 SPI
 117    FSPI_PORT_DIR &= ~(FSPI_DI | FSPI_DO | FSPI_CLK | SAMPLE_VALID); // set all as inputs
 118  }
 119  
 120  /**
 121   \Brief Sends and receives 16bits over spi
 122   **/
 123  inline unsigned int FSPI_write_wait_read(unsigned int datain)
 124  {
 125    unsigned int result;
 126  
 127    FSPI_TX_BUF = datain >> 8;                  // send first half, MSB first
 128    while (FSPI_BUSY) WDG_reset();
 129    result = ((unsigned int) FSPI_RX_BUF) << 8; // read first half, MSB first
 130  
 131    FSPI_TX_BUF = datain;
 132    while (FSPI_BUSY) WDG_reset();
 133    return result | FSPI_RX_BUF;
 134  }
 135  
 136