Accelerated Network Technologies

Technology / Pattern Matching

Author: Jan Kořenek ()
Update: 1.2.2012

Pattern matching is task mainly used in IDS and IPS systems for detection of malicious network traffic by set of patterns, which are often described by strings or rugular expressions. Current processors are not able to achieve multi-gigabit speed for large set of strings or regular expressions even if they use the fastest algorithms. Therefore many hardware architectures have been proposed for a string or a regular expression matching. Unfortunately all these architectures are able to achieve a high throughput only for small sets of regular expressions. The capacity and the speed of available memories is a limitation for architectures based on a deterministic finite automaton and the capacity of available FPGA chips is a limitation for architectures based on a nondeterministic finite automaton. Therefore our goal is reduce the amount of consumed FPGA logic for a high speed regular expression matching using a nondeterministic automaton and reduce memory requirements for a high speed regular expression matching using a deterministic automaton.

List of Publications

  • Košař Vlastimil, Kořenek Jan: Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, s. 401-402, ISBN 978-1-4244-9753-9

  • Kořenek Jan, Košař Vlastimil: Architektura NFA Split pro rychlé hledání regulárních výrazů, In: Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, La Jolla, US, ACM, 2010, s. 2, ISBN 978-1-4503-0379-8

  • Kořenek Jan, Košař Vlastimil: Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching, In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, Vienna, AT, IEEE CS, 2010, s. 6, ISBN 978-1-4244-6610-8

  • Kaštil Jan, Kořenek Jan: Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing, In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, Vienna, AT, 2010, p. 149-152, ISBN 978-1-4244-6610-8

  • Kaštil Jan, Kořenek Jan: High Speed Pattern Matching Algorithm Based on Deterministic Finite Automata with Faulty Transition Table, In: Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, La Jolla, US, ACM, 2010, p. 2, ISBN 978-1-4503-0379-8

  • Kaštil Jan, Kořenek Jan, Lengál Ondřej: Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing, In: 12th EUROMICRO Conference on Digital System Design DSD 2009, Patras, GR, IEEE CS, 2009, p. 823-289, ISBN 978-0-7695-3782-5

  • Kaštil Jan, Kořenek Jan: Deterministic Finite Automaton with Perfect Hashing for Fast Pattern Matching, In: Proceedings of Junior Scientist Conference 2008, Vienna, AT, TU-Wien, 2008, p. 103-104, ISBN 978-3-200-01612-5

  • Kobierský Petr, Kořenek Jan, Hank Andrej: Traffic Scanner, Příbram, CZ, CESNET, 2007, s. 55-67, ISBN 978-80-239-9285-4

  • Kořenek Jan, Kobierský Petr: Intrusion Detection System Intended for Multigigabit Networks, In: 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, PL, IEEE CS, 2007, p. 361-364, ISBN 1-4244-1161-0

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