Accelerated Network Technologies

Technology / NetCOPE Platform

Author: Tomáš Martínek ()
Update: 2.11.2009

NetCOPE is a platform dedicated for acceleration of network applications using FPGA technology. Such an accelerated network application is usually composed of two parts: 1) Acceleration core – which is placed inside FPGA chip and implements time critical parts of application such as header field extraction, classification process, patter matching etc.; 2) Software part of application – usually provides management and control function. NetCOPE covers both – hardware and software part of the platform and precisely defines the general interface between them.

The hardware part of the NetCOPE platform includes:

  • IO/Blocks - components implementing packet receiving and transmitting via Ethernet protocol in compliance with standard IEEE 802.3. In the basic implementation, the blocks for 1Gbps and 10Gbps link rate are supported.

  • Interconnection System - provides the communication between components placed in FPGA and a system bus (PCI, PCI-X or PCI Express). It is capable to process read and write transactions incoming from a system bus and distribute them to individual components in FPGA (Slave mode). Similarly in the opposite direction, it propagates read and write transactions from components to a system bus (Bus Master mode).,

  • Fast DMA Controllers – components, that realize fast DMA transfers between acceleration core and the host RAM.

Fast DMA transfers between acceleration core and the host RAM represents one of the most important feature of the NetCOPE platform. Their realization is based on data transfers between two ring buffers. The first one is placed in the host RAM and is used for accessing data from the side of the software application or threads. The buffer memory space is physically split into the 4kB pages and continuously mapped into the application address space via system call mmap(). The second buffer is inside FPGA chip (DMA buffer) and make data available for an acceleration core.

Software part the of the NetCOPE platform includes driver and auxiliary libsze library, which allows to software application to access data transferred to or from acceleration core easily.

netcope_arch.png

Figure 1.1: NetCOPE Architecture

List of Publications

  • Málek Tomáš, Martínek Tomáš, Kořenek Jan: GICS: Generic Interconnection System, In: 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, DE, IEEE CS, 2008, s. 263-268, ISBN 978-1-4244-1961-6

  • Martínek Tomáš, Košek Martin: NetCOPE: Platform for Rapid Development of Network Applications, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, s. 219-224, ISBN 978-1-4244-2276-0

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