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fspi.c

   1  /*******************************************************************************
   2     fspi.c: second SPI interface
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5     Author(s): Karel Slany <slany AT fit.vutbr.cz>
   6  
   7     LICENSE TERMS
   8  
   9     Redistribution and use in source and binary forms, with or without
  10     modification, are permitted provided that the following conditions
  11     are met:
  12     1. Redistributions of source code must retain the above copyright
  13        notice, this list of conditions and the following disclaimer.
  14     2. Redistributions in binary form must reproduce the above copyright
  15        notice, this list of conditions and the following disclaimer in
  16        the documentation and/or other materials provided with the
  17        distribution.
  18     3. All advertising materials mentioning features or use of this software
  19        or firmware must display the following acknowledgement:
  20  
  21          This product includes software developed by the University of
  22          Technology, Faculty of Information Technology, Brno and its
  23          contributors.
  24  
  25     4. Neither the name of the Company nor the names of its contributors
  26        may be used to endorse or promote products derived from this
  27        software without specific prior written permission.
  28  
  29     This software or firmware is provided ``as is'', and any express or implied
  30     warranties, including, but not limited to, the implied warranties of
  31     merchantability and fitness for a particular purpose are disclaimed.
  32     In no event shall the company or contributors be liable for any
  33     direct, indirect, incidental, special, exemplary, or consequential
  34     damages (including, but not limited to, procurement of substitute
  35     goods or services; loss of use, data, or profits; or business
  36     interruption) however caused and on any theory of liability, whether
  37     in contract, strict liability, or tort (including negligence or
  38     otherwise) arising in any way out of the use of this software, even
  39     if advised of the possibility of such damage.
  40  
  41     $Id$
  42  
  43  
  44  *******************************************************************************/
  45  
  46  #include "fspi.h"
  47  
  48  /**
  49   \brief SPI initialization
  50   **/
  51  void FSPI_Init(char smclkdiv)
  52  {
  53   #if defined MSP_16X
  54      while(1) {} //FITkit 1.x not supported
  55  
  56    /*
  57    // set SPI to UART0 (FITkit 1.x)
  58  
  59    U0CTL |= SWRST;                   /// reset SPI
  60    U0CTL = SWRST | CHAR | SYNC | MM; /// SPI mode, 8 bit, master mode
  61    U0TCTL = CKPL | SSEL_3 | STC;     /// SMCLK clock (7MHz), idle polarity 1
  62    U0BR0 = 2;                        /// max speed (SMCLK/2)
  63    U0BR1 = 0;
  64    ME2 |= USPIE1;                    /// enable SPI
  65  
  66    // I/O setup
  67    FSPI_PORT_DIR &= ~(FSPI_DI);         // inputs
  68    FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK; // outputs
  69    FSPI_PORT_OUT |= FSPI_DO | FSPI_CLK; // set outputs to 1
  70  
  71    FSPI_PORT_SEL |= FSPI_DI | FSPI_DO | FSPI_CLK; // connects pins to  USART
  72  
  73    U0CTL &= ~SWRST; // enable SPI (disable reset)
  74    */
  75   #elif defined MSP_261X
  76    // set SPI to UCB0 (FITkit 2.x)
  77  
  78    UCB0CTL1 = UCSWRST; /// reset UCB0
  79  
  80    UCB0CTL0 = UCCKPH | UCMST | UCMSB | UCMODE_0 | UCSYNC; /// SPI mode, 8 bit, master mode, msb first, idle polarity 0
  81    UCB0CTL1 |= UCSSEL_2;                                  /// SMCLK clock
  82    UCB0BR0 = smclkdiv;                                    /// speed SMCLK/smclkdiv = 14/smclkdiv MHz
  83    UCB0BR1 = 0;
  84  
  85    // I/O setup
  86    FSPI_PORT_DIR &= ~(FSPI_DI);         // inputs
  87    FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK | FSPI_CS; // outputs
  88    FSPI_PORT_OUT &= ~FSPI_CLK; // set outputs to 0
  89    FSPI_PORT_OUT |= FSPI_DO | FSPI_CS; // set outputs to 1
  90  
  91    FSPI_PORT_SEL |= SPI_DI | SPI_DO | SPI_CLK; // connects pins to UCB0
  92  
  93    //UC1IFG = 0;
  94    UC0IE &= ~(UCB0TXIE | UCB0RXIE);
  95  
  96    UCB0CTL1 &= ~UCSWRST; // disable UCB0 reset
  97   #else
  98    #error "Can't initialize SPI"
  99   #endif
 100  }
 101  
 102  
 103  /**
 104   \brief Disables SPI
 105   **/
 106  void FSPI_Close(void)
 107  {
 108   #if defined MSP_16X
 109    /*
 110    // disable SPI
 111    ME2 &= ~USPIE1; // enable SPI
 112    U0CTL = SWRST;  // disable (reset) SPI
 113    */
 114   #elif defined MSP_261X
 115    UCB0CTL1 |= UCSWRST; /// reset UCB0
 116   #endif
 117  
 118    // disable I/O
 119    FSPI_PORT_SEL &= ~(FSPI_DI | FSPI_DO | FSPI_CLK);                // disconnect pins USART0 SPI
 120    FSPI_PORT_DIR &= ~(FSPI_DI | FSPI_DO | FSPI_CLK | FSPI_CS); // set all as inputs
 121  }
 122  
 123  /**
 124   \Brief Sends and receives 8bits over SPI
 125   **/
 126  inline unsigned char FSPI_write_wait_read(unsigned char data)
 127  {
 128    FSPI_TX_BUF = data;
 129    while (FSPI_BUSY) {WDG_reset();}
 130    return FSPI_RX_BUF;
 131  }
 132  
 133  /**
 134   \Brief Sends and receives 8bits over SPI
 135   **/
 136  inline void FSPI_write_wait(unsigned char data)
 137  {
 138    FSPI_TX_BUF = data;
 139    while (FSPI_BUSY) {WDG_reset();}
 140  }
 141  
Zobrazeno: 597135x Naposledy: 27.1.2022 15:07:23