Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / mcu / libs / enc28j60 /

enc28j60_spi.c

   1  /*******************************************************************************
   2  
   3     Copyright (C) 2010 Brno University of Technology,
   4                        Faculty of Information Technology
   5     Author(s): Martin Musil <xmusil34 AT fit.vutbr.cz>
   6  
   7     LICENSE TERMS
   8  
   9     Redistribution and use in source and binary forms, with or without
  10     modification, are permitted provided that the following conditions
  11     are met:
  12     1. Redistributions of source code must retain the above copyright
  13        notice, this list of conditions and the following disclaimer.
  14     2. Redistributions in binary form must reproduce the above copyright
  15        notice, this list of conditions and the following disclaimer in
  16        the documentation and/or other materials provided with the
  17        distribution.
  18     3. All advertising materials mentioning features or use of this software
  19        or firmware must display the following acknowledgement:
  20  
  21          This product includes software developed by the University of
  22          Technology, Faculty of Information Technology, Brno and its
  23          contributors.
  24  
  25     4. Neither the name of the Company nor the names of its contributors
  26        may be used to endorse or promote products derived from this
  27        software without specific prior written permission.
  28  
  29     This software or firmware is provided ``as is'', and any express or implied
  30     warranties, including, but not limited to, the implied warranties of
  31     merchantability and fitness for a particular purpose are disclaimed.
  32     In no event shall the company or contributors be liable for any
  33     direct, indirect, incidental, special, exemplary, or consequential
  34     damages (including, but not limited to, procurement of substitute
  35     goods or services; loss of use, data, or profits; or business
  36     interruption) however caused and on any theory of liability, whether
  37     in contract, strict liability, or tort (including negligence or
  38     otherwise) arising in any way out of the use of this software, even
  39     if advised of the possibility of such damage.
  40  
  41     $Id$
  42  
  43  *******************************************************************************/
  44  
  45  #include "enc28j60_spi.h"
  46  #include "enc28j60_arp.h"
  47  #include "fspi.h"
  48  
  49  
  50  unsigned char current_bank = 0;
  51  extern unsigned char local_mac[MAC_LEN];
  52  extern unsigned int rx_next_pkt;
  53  char enc_initialized = 0;
  54  /**
  55   \brief Inicializace a start ENC28J60
  56   **/
  57  char ENC28J60_init(){
  58  
  59  	FSPI_Init(1); //14MHz SPI
  60  	delay_ms(10);
  61  	control_reg_write(0x01); //EN = 1, RST=0
  62  	delay_ms(10);
  63  	control_reg_write(0x03); //EN = 1, RST=1
  64  	delay_ms(10);
  65  
  66  	enc_reset();
  67  	delay_ms(10);
  68  
  69  	bf_clear(ECON1, ECON1_RXEN);
  70  
  71  	select_bank(0);
  72  	write_reg16(ERXST,RX_START);		//zacatek RX bufferu
  73  	write_reg16(ERXND,RX_END);			//konec RX bufferu
  74  	write_reg16(ERXRDPT,RX_END);		//ptr pro cteni z bufferu
  75  	write_reg16(ERDPT,RX_START);		//ptr pro zapis do bufferu
  76  
  77  	arp_table_clear();
  78  	rx_next_pkt = RX_START;
  79  
  80  	bf_set(ECON2, ECON2_AUTOINC);		//autoinkrementace buffer-pointeru a
  81  	bf_clear(ECON2,ECON2_PWRSV);		//probuzeni
  82  	delay_ms(10);						//cekani na ustaleni oscilatoru
  83  
  84  
  85  	select_bank(1);
  86  	write_reg8(ERXFCON, 0xA1);			//vstupni filter - uni/broadcast
  87  
  88  	select_bank(2);						//banka 2
  89  	//inicializace MAC
  90  	write_reg8(MACON2,0);
  91  	write_reg8(MACON1,MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);	//nastaveni TXPAUS, RXPAUS, MARXEN
  92  	write_reg8(MACON3,MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FULDPX);	//nastaveni PADCFG, TXCRCEN, FULDPX
  93  	write_reg8(MACON4,MACON4_DEFER);		//nastaveni DEFER
  94  
  95  	write_reg16(MAMXFL,0x05EE);			//max. velikost ramce 1518B
  96  	write_reg8(MABBIPG,0x15);					//Back-to-Back Inter-Packet Gap - pro full duplex
  97  	write_reg8(MAIPGL, 0x12);
  98  
  99  	write_phy_reg16(PHCON1,PHCON1_PDPXMD);  //pro full duplex
 100  
 101  	write_phy_reg16(PHIE, PHIE_PLNKIE | PHIE_PGEIE);
 102  	read_phy_reg16(PHIR);
 103  
 104  	select_bank(3);		   				//banka 3
 105  	write_reg8(MAADR1, local_mac[0]);	//nastaveni MAC adresy
 106  	write_reg8(MAADR2, local_mac[1]);
 107  	write_reg8(MAADR3, local_mac[2]);
 108  	write_reg8(MAADR4, local_mac[3]);
 109  	write_reg8(MAADR5, local_mac[4]);
 110  	write_reg8(MAADR6, local_mac[5]);
 111  
 112  	write_reg8(EIE,0);					//zakazani preruseni
 113  	bf_set(ECON1, ECON1_RXEN);			//povoleni vstupu
 114  
 115  	enc_initialized = 1;
 116  
 117  return 0;
 118  }
 119  
 120  
 121  
 122  /**
 123  
 124   **/
 125  inline unsigned char read_reg8(unsigned char addr, unsigned char read_dummy){
 126  
 127  	unsigned char data;
 128  
 129  	FSPI_set_CS(0); //CS -> 0
 130  	FSPI_write_wait(ENC_RCR | addr);
 131  
 132  	if (read_dummy)
 133  		FSPI_write_wait(DUMMY);
 134  
 135  	data = FSPI_write_wait_read(DUMMY);
 136  	FSPI_set_CS(1); //CS -> 1
 137  
 138     return data;
 139  }
 140  
 141  /**
 142  
 143   **/
 144  inline unsigned int read_reg16(unsigned char addr, unsigned char read_dummy){
 145  
 146  return read_reg8(addr,read_dummy) | (read_reg8(addr+1,read_dummy) << 8);
 147  }
 148  
 149  /**
 150  
 151   **/
 152  inline void write_reg8(unsigned char addr, unsigned char data){
 153  	FSPI_set_CS(0); //CS -> 0
 154  	FSPI_write_wait(ENC_WCR | addr);
 155  	FSPI_write_wait(data);
 156  	FSPI_set_CS(1); //CS -> 1
 157  return;
 158  }
 159  
 160  /**
 161  
 162   **/
 163  inline void write_reg16(unsigned char addr, unsigned int data){
 164  
 165  	write_reg8(addr,(char)data);
 166  	write_reg8(addr+1,(char)(data>>8));
 167  
 168  }
 169  
 170  /**
 171  
 172   **/
 173  inline int read_phy_reg16(unsigned char addr){
 174  
 175  	select_bank(2);
 176  	write_reg8(MIREGADR, addr);
 177  	write_reg8(MICMD, MICMD_MIIRD);
 178  
 179   	while(read_reg8(MISTAT,DUMMY) & MISTAT_BUSY);
 180  	write_reg8(MICMD, 0);
 181  
 182  return read_reg16(MIRD,DUMMY);
 183  }
 184  
 185  /**
 186  
 187   **/
 188  inline void write_phy_reg16(unsigned char addr, unsigned int data){
 189  
 190  	select_bank(2);
 191  	write_reg8(MIREGADR, addr);
 192  	write_reg16(MIWR, data);
 193  
 194  return;
 195  }
 196  
 197  /**
 198  
 199   **/
 200  inline void bf_set(unsigned char addr, unsigned char mask){
 201     FSPI_set_CS(0); //CS -> 0
 202     FSPI_write_wait(ENC_BFS | addr);
 203     FSPI_write_wait(mask);
 204     FSPI_set_CS(1); //CS -> 1
 205  }
 206  
 207  /**
 208   \brief BFC (Bit Field Clear) - Vynuluje bity v registru podle masky, operace NOT AND
 209   **/
 210  inline void bf_clear(unsigned char addr, unsigned char mask){
 211     FSPI_set_CS(0); //CS -> 0
 212     FSPI_write_wait(ENC_BFC | addr);
 213     FSPI_write_wait(mask);
 214     FSPI_set_CS(1); //CS -> 1
 215  }
 216  
 217  /**
 218   \brief Resetuje ENC28J60
 219   **/
 220  inline void enc_reset(){
 221     FSPI_set_CS(0); //CS -> 0
 222     FSPI_write_wait(ENC_RST);
 223     FSPI_set_CS(1); //CS -> 1
 224     enc_initialized = 0;
 225  }
 226  
 227  /**
 228  
 229   **/
 230  inline void select_bank(unsigned char bank){
 231  
 232  	if(bank < 4 && current_bank != bank){
 233  		current_bank = bank;
 234  		bf_clear(ECON1, 0x03);
 235  		bf_set(ECON1, bank);
 236  	}
 237  return;
 238  }
 239  
 240  
 241  //******************************************
 242  //fce cteni/zapis do bufferu
 243  //******************************************
 244  
 245  /**
 246  
 247   **/
 248  unsigned char spi_getc(){
 249  
 250  	unsigned char data;
 251  
 252  	FSPI_set_CS(0); //CS -> 0
 253  	FSPI_write_wait(ENC_RBM);
 254  	data = FSPI_write_wait_read(DUMMY);
 255  	FSPI_set_CS(1); //CS -> 1
 256  
 257     return data;
 258  }
 259  
 260  /**
 261  
 262   **/
 263  unsigned int spi_read(void* ptr, unsigned int length){
 264  
 265  	if(ptr != NULL){						//cteni do pole
 266  		unsigned char* ptr_temp = ptr;
 267  
 268  		FSPI_set_CS(0); //CS -> 0
 269  		FSPI_write_wait(ENC_RBM);
 270  
 271  		while(length--)
 272  			*ptr_temp++ = FSPI_write_wait_read(DUMMY);
 273  
 274  		FSPI_set_CS(1); //CS -> 1
 275  	}
 276  	else{									//zahazovani
 277  		FSPI_set_CS(0); //CS -> 0
 278  		FSPI_write_wait(ENC_RBM);
 279  
 280  		while(length--)
 281  			FSPI_write_wait_read(DUMMY);
 282  
 283  		FSPI_set_CS(1); //CS -> 1
 284  	}
 285  return length;
 286  }
 287  
 288  /**
 289  
 290  
 291   **/
 292  unsigned int spi_getline(void* ptr, unsigned int max_length){
 293  
 294  	unsigned char c;
 295  	unsigned int countdown = max_length;
 296  
 297  	if(ptr != NULL){						//cteni do pole
 298  		unsigned char* ptr_temp = ptr;
 299  
 300  		FSPI_set_CS(0); //CS -> 0
 301  		FSPI_write_wait(ENC_RBM);
 302  
 303  
 304  		while(countdown != 0){
 305  			c = FSPI_write_wait_read(DUMMY);
 306  			*ptr_temp++ = c;
 307  			countdown--;
 308  
 309  			if(c == 10)						// 10 - Line Feed
 310  				break;
 311  		}
 312  		FSPI_set_CS(1); //CS -> 1
 313  	}
 314  	else{									//zahazovani
 315  		FSPI_set_CS(0); //CS -> 0
 316  		FSPI_write_wait(ENC_RBM);
 317  
 318  		while(countdown != 0){
 319  			c = FSPI_write_wait_read(DUMMY);
 320  			countdown--;
 321  
 322  			if(c == 10)						// 10 - Line Feed
 323  				break;
 324  		}
 325  		FSPI_set_CS(1); //CS -> 1
 326  	}
 327  
 328  return max_length - countdown;
 329  }
 330  
 331  /**
 332  
 333   **/
 334  void spi_putc(unsigned char c){
 335  
 336  	FSPI_set_CS(0); //CS -> 0
 337  	FSPI_write_wait(ENC_WBM);
 338  	FSPI_write_wait(c);
 339  
 340  	FSPI_set_CS(1); //CS -> 1
 341  
 342  }
 343  
 344  /**
 345  
 346   **/
 347  void spi_write(void* ptr, unsigned int length){
 348  
 349  	unsigned char* ptr_temp = ptr;
 350  
 351  	FSPI_set_CS(0); //CS -> 0
 352  	FSPI_write_wait(ENC_WBM);
 353  
 354  	while(length--)
 355  		FSPI_write_wait(*ptr_temp++);
 356  
 357  	FSPI_set_CS(1); //CS -> 1
 358  
 359  }
 360  
 361  /**
 362  
 363   **/
 364  void spi_fill(unsigned char value, unsigned int length){
 365  
 366  	FSPI_set_CS(0); //CS -> 0
 367  	FSPI_write_wait(ENC_WBM);
 368  
 369  	while(length--)
 370  		FSPI_write_wait(value);
 371  
 372  	FSPI_set_CS(1); //CS -> 1
 373  }
 374  
 375  /**
 376  
 377   **/
 378  inline unsigned char link_change(){
 379  
 380  	if((read_reg8(EIR,NO_DUMMY) & EIR_LINKIF) > 0){
 381  		read_phy_reg16(PHIR);
 382  		return 1;
 383  	}
 384  
 385  return 0;
 386  }
 387  
 388  /**
 389  
 390   **/
 391  inline unsigned char link_up(){
 392  
 393  	//read_phy_reg16(PHIR);			//smazani priznaku zmeny linky
 394  
 395  	if((read_phy_reg16(PHSTAT2) & PHSTAT2_LSTAT) == 0 ){		//kabel odpojen
 396  		return 0;
 397  	}
 398  
 399  return 1;
 400  }
 401  
 402  
Zobrazeno: 683866x Naposledy: 5.7.2022 06:10:03