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Aktuální adresář: FITkit / trunk / mcu / libs / codec /

audio_codec.h

   1  /*******************************************************************************
   2     audio_codec.h: FITKit 2.0 codec control functions
   3     Copyright (C) 2009 Brno University of Technology,
   4                        Faculty of Information Technology
   5     Author(s): Karel Slany <slany AT fit.vutbr.cz>
   6  
   7     LICENSE TERMS
   8  
   9     Redistribution and use in source and binary forms, with or without
  10     modification, are permitted provided that the following conditions
  11     are met:
  12     1. Redistributions of source code must retain the above copyright
  13        notice, this list of conditions and the following disclaimer.
  14     2. Redistributions in binary form must reproduce the above copyright
  15        notice, this list of conditions and the following disclaimer in
  16        the documentation and/or other materials provided with the
  17        distribution.
  18     3. All advertising materials mentioning features or use of this software
  19        or firmware must display the following acknowledgement:
  20  
  21          This product includes software developed by the University of
  22          Technology, Faculty of Information Technology, Brno and its
  23          contributors.
  24  
  25     4. Neither the name of the Company nor the names of its contributors
  26        may be used to endorse or promote products derived from this
  27        software without specific prior written permission.
  28  
  29     This software or firmware is provided ``as is'', and any express or implied
  30     warranties, including, but not limited to, the implied warranties of
  31     merchantability and fitness for a particular purpose are disclaimed.
  32     In no event shall the company or contributors be liable for any
  33     direct, indirect, incidental, special, exemplary, or consequential
  34     damages (including, but not limited to, procurement of substitute
  35     goods or services; loss of use, data, or profits; or business
  36     interruption) however caused and on any theory of liability, whether
  37     in contract, strict liability, or tort (including negligence or
  38     otherwise) arising in any way out of the use of this software, even
  39     if advised of the possibility of such damage.
  40  
  41     $Id$
  42  
  43  
  44  *******************************************************************************/
  45  
  46  

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#ifndef _AUDIO_CODEC_H_ 47

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#define _AUDIO_CODEC_H_ 48 49

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#if defined MSP_16X 50 //#error "Codec not present on this version of FITKit" 51

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#elif defined MSP_261X 52

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#endif 53 54

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#define ADDRMASK 0x7F 55

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#define DATAMASK 0x1FF 56

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#define DATABITS 9 57

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#define codec_join_addr_data(addr, data) ((((unsigned int)(addr) & ADDRMASK) << DATABITS) | ((unsigned int)(data) & DATAMASK)) 58 59 /* 16 bits are send via the SPI interface to the device 60 * MSB LSB 61 * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 62 * | 7bit register address | 9bit control data | 63 */ 64 65 /* codec control register SPI addresses (7 bits) */ 66

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#define LINE_IN_VOL_L 0x00 /* left line input channel volume control */ 67

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#define LINE_IN_VOL_R 0x01 /* right line input channel volume control */ 68

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#define HPHONE_OUT_VOL_L 0x02 /* left channel headphone volume control */ 69

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#define HPHONE_OUT_VOL_R 0x03 /* right channel headphone volume control */ 70

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#define ALOG_PATH_CTRL 0x04 /* analog audio path control */ 71

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#define DTAL_PATH_CTRL 0x05 /* digital audio path control */ 72

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#define PWR_DWN_CTRL 0x06 /* power down control */ 73

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#define DTAL_IFACE_FMAT 0x07 /* digital audio interface format */ 74

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#define SRATE_CTRL 0x08 /* sample rate control */ 75

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#define DTAL_IFACE_ACT 0x09 /* digital interface activation */ 76

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#define RST_REG 0x0F /* reset register */ 77 78 /* left line input channel volume control (9 bits) 79 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 80 * | LRS | LIM | X | X | LIV | 81 * default 82 * 0 1 0 0 1 0 1 1 1 83 */ 84

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#define LRS 0x100 /* left/right line simultaneous volume/mute update; 1 - enabled */ 85

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#define LRS_on LRS 86

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#define LRS_off 0x000 87

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#define LIM 0x080 /* left line input mute; 1 - muted */ 88

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#define LIM_on LIM 89

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#define LIM_off 0x000 90 //#define LRES 0x060 /* left control reserved bits */ 91

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#define LIV 0x01F /* left line input volume control (1.5dB step); 10111 - default */ 92

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#define LIV_GAIN_Z 0x017 /* 10111 = 0dB */ 93

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#define LIV_GAIN_MAX LIV /* 11111 = +12dB */ 94

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#define LIV_GAIN_MIN 0x000 /* 00000 = -34.5dB */ 95 96 /* right line input channel volume control (9 bits) 97 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 98 * | RLS | RIM | X | X | RIV | 99 * default 100 * 0 1 0 0 1 0 1 1 1 101 */ 102

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#define RLS 0x100 /* right/left line simultaneous volume/mute update; 1 - enabled */ 103

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#define RLS_on RLS 104

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#define RLS_off 0x000 105

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#define RIM 0x080 /* right line input mute; 1 - muted */ 106

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#define RIM_on RIM 107

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#define RIM_off 0x000 108 //#define RRES 0x060 /* right control reserved bits */ 109

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#define RIV 0x01F /* right line input volume control (1.5dB step); 10111 - default */ 110

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#define RIV_GAIN_Z 0x017 /* 10111 = 0dB */ 111

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#define RIV_GAIN_MAX RIV /* 11111 = +12dB */ 112

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#define RIV_GAIN_MIN 0x000 /* 00000 = -34.5dB */ 113 114 /* left channel headphone volume control (9 bits) 115 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 116 * | LRS | LZC | LHV | 117 * default 118 * 0 1 1 1 1 1 0 0 1 119 */ 120 //#define LRS 0x100 /* left/right headphone channel simultaneous volume/mute update; 1 - enabled */ 121

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#define LZC 0x080 /* left-channel zero-cross detect */ 122

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#define LZC_on LZC 123

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#define LZC_off 0x000 124

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#define LHV 0x07F /* left headphone volume control (79 steps); 1111001 - default */ 125

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#define LHV_GAIN_Z 0x079 /* 1111001 = 0dB */ 126

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#define LHV_GAIN_MAX LHV /* 1111111 = +6dB */ 127

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#define LHV_GAIN_MIN 0x030 /* 0110000 = -73dB; any below this value doe nothing - still muted */ 128 129 /* right channel headphone volume control 130 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 131 * | RLS | RZC | RHV | 132 * default 133 * 0 1 1 1 1 1 0 0 1 134 */ 135 //#define RLS 0x100 /* right/left headphone channel simultaneous volume/mute update; 1 - enabled */ 136

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#define RZC 0x080 /* right-channel zero-cross detect */ 137

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#define RZC_on RZC 138

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#define RZC_off 0x000 139

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#define RHV 0x07F /* right headphone volume control (79 steps); 1111001 - default */ 140

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#define RHV_GAIN_Z 0x079 /* 1111001 = 0dB */ 141

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#define RHV_GAIN_MAX LHV /* 1111111 = +6dB */ 142

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#define RHV_GAIN_MIN 0x030 /* 0110000 = -73dB; any below this value doe nothing - still muted */ 143 144 /* analog audio path control (9 bits) 145 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 146 * | STA | STE | DAC | BYP |INSEL|MICM |MICB | 147 * default 148 * 0 0 0 0 0 1 0 1 0 149 */ 150

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#define STA2 0x100 151

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#define STA1 0x080 152

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#define STA0 0x040 153

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#define STE 0x020 /* STE STA2 STA1 STA0 | added sidetone */ 154

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#define ST_minus0dB 0x120 /* 1 1 X X | 0dB */ 155

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#define ST_minus6dB 0x020 /* 1 0 0 0 | -6dB */ 156

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#define ST_minus9dB 0x060 /* 1 0 0 1 | -9dB */ 157

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#define ST_minus12dB 0x0A0 /* 1 0 1 0 | -12dB */ 158

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#define ST_minus18dB 0x0E0 /* 1 0 1 1 | -18dB */ 159

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#define ST_disable 0x000 /* 0 X X X | disabled */ 160

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#define DAC 0x010 /* DAC selected; 1 = DAC selected */ 161

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#define DAC_on DAC 162

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#define DAC_off 0x000 163

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#define BYP 0x008 /* bypass, 1 = enabled */ 164

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#define BYP_on BYP 165

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#define BYP_off 0x000 166

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#define INSEL 0x004 /* input select for DAC; 0 = line, 1 = microphone */ 167

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#define INSEL_line 0x000 168

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#define INSEL_mic INSEL 169

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#define MICM 0x002 /* microphone mute; 1 = muted */ 170

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#define MICM_on MICM 171

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#define MICM_off 0x000 172

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#define MICB 0x001 /* microphone boost; 0 = 0dB, 1 = +20dB */ 173

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#define MICB_on MICB 174

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#define MICB_off 0x000 175 176 /* digital audio path control (9 bits) 177 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 178 * | X | X | X | X | X |DACM | DEEMP |ADCHP| 179 * default 180 * 0 0 0 0 0 1 0 0 0 181 */ 182 //#define DAPRES 0x1F0 /* reserved bits */ 183

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#define DACM 0x008 /* DAC soft mute; 1 = enabled */ 184

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#define DACM_on DACM 185

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#define DACM_off 0x000 186

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#define DEEMP 0x006 /* de-emphasis control */ 187

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#define DEEMP_disabled 0x000 /* 00 - disabled */ 188

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#define DEEMP_32kHz 0x002 /* 01 - 32kHz */ 189

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#define DEEMP_44k1Hz 0x004 /* 10 - 44.1kHz */ 190

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#define DEEMP_48kHz DEEMP /* 11 - 48kHz */ 191

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#define ADCHP 0x001 /* ADC high-pass filter; 0 - enabled; 1 - disabled */ 192

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#define ADCHP_on 0x000 193

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#define ADCHP_off ADCHP 194 195 /* power down control (9 bits) 196 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 197 * | X | OFF | CLK | OSC | OUT | DAC | ADC | MIC |LINE | 198 * default 199 * 0 0 0 0 0 0 1 1 1 200 */ 201 //#define PDCRES 0x100 /* reserved bits */ 202

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#define CODEC_OFF 0x080 /* device power; 0 = on, 1 = off */ 203

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#define CODEC_ON 0x000 204

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#define CODEC_CLK 0x040 /* clock; 0 = on; 1 = off */ 205

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#define CODEC_CLK_on 0x000 206

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#define CODEC_CLK_off CODEC_CLK 207

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#define CODEC_OSC 0x020 /* oscillator; 0 = on, 1 = off */ 208

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#define CODEC_OSC_on 0x000 209

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#define CODEC_OSC_off CODEC_OSC 210

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#define CODEC_OUT 0x010 /* outputs; 0 = on, 1 = off */ 211

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#define CODEC_OUT_on 0x000 212

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#define CODEC_OUT_off CODEC_OUT 213

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#define CODEC_DAC 0x008 /* DAC; 0 = on, 1 = off */ 214

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#define CODEC_DAC_on 0x000 215

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#define CODEC_DAC_off CODEC_DAC 216

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#define CODEC_ADC 0x004 /* ADC; 0 = on; 1 = off */ 217

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#define CODEC_ADC_on 0x000 218

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#define CODEC_ADC_off CODEC_ADC 219

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#define CODEC_MIC 0x002 /* microphone input; 0 = off, 1 = on */ 220

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#define CODEC_MIC_on 0x000 221

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#define CODEC_MIC_off CODEC_MIC 222

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#define CODEC_LINE 0x001 /* line input; 0 = on, 1 = off */ 223

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#define CODEC_LINE_on 0x000 224

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#define CODEC_LINE_off CODEC_LINE 225 226 /* digital audio interface format (9 bits) 227 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 228 * | X | X | MS |LRSWAP| LRP | IWL | FOR | 229 * default 230 * 0 0 0 0 0 0 0 0 1 231 */ 232 //#define DAIFRES 0x180 /* reserved bits */ 233

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#define MS 0x040 /* master/slave mode; 0 = slave; 1 = master */ 234

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#define MS_slave 0x000 235

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#define MS_master MS 236

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#define LRSWAP 0x020 /* DAC left/right swap; 1 = enabled */ 237

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#define LRSWAP_on LRSWAP 238

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#define LRSWAP_off 0x000 239

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#define LRP 0x010 /* left/right phase */ 240

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#define LRP_on LRP /* 0 = right channel on, LRCIN high; in DSP mode - MSB is 241 * available on 1st BCLK rising edge after LRCIN rising edge */ 242

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#define LRP_off 0x000 /* 1 = right channel on, LRCIN low; in DSP mode - MSB is 243 * available on 2nd BCLK rising edge after LRCIN rising edge */ 244

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#define IWL 0x00C /* input bit length */ 245

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#define IWL_16bit 0x000 /* 00 - 16bit */ 246

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#define IWL_20bit 0x004 /* 01 - 20bit */ 247

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#define IWL_24bit 0x008 /* 10 - 24bit */ 248

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#define IWL_32bit IWL /* 11 - 32bit */ 249

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#define FOR 0x003 /* data format */ 250

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#define FOR_DSP FOR /* 11 - DSP format, frame sync followed by two data words */ 251

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#define FOR_I2S 0x002 /* 10 - I2S format, MSB first, left - 1 aligned */ 252

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#define FOR_left 0x001 /* 01 - MSB first, left aligned */ 253

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#define FOR_right 0x000 /* 00 - MSB first, right aligned */ 254 255 /* sample rate control (9 bits) 256 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 257 * | X |CLKOUT|CLKIN| SR |BOSR |USB/normal| 258 * default 259 * 0 0 0 1 0 0 0 0 0 260 */ 261 //#define SRCRES 0x100 /* reserved bits */ 262

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#define CLKOUT 0x080 /* clock output divider; 0 = MCLK, 1 = MCLK/2 */ 263

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#define CLKOUT_full 0x000 264

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#define CLKOUT_half CLKOUT 265

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#define CLKIN 0x040 /* clock input divider; 0 = MCLK, 1 = MCLK/2 */ 266

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#define CLKIN_full 0x000 267

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#define CLKIN_half CLKIN 268

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#define SR 0x03C /* sampling rate control - see datasheet */ 269

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#define BOSR 0x002 /* base oversampling rate */ 270 /* for SR and BOSR settings see datasheet */ 271 272 /* USB mode */ 273

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#define USB_ADC96k_DAC96k 0x01C 274

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#define USB_ADC88k2_DAC88k2 0x03E 275

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#define USB_ADC48k_DAC48k 0x000 276

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#define USB_ADC44k1_DAC44k1 0x022 277

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#define USB_ADC32k_DAC32k 0x018 278

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#define USB_ADC8k021_DAC8k021 0x02E 279

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#define USB_ADC8k_DAC8k 0x00C 280 281 /* normal mode - MCLK = 12.288MHz */ 282

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#define N12_ADC96k_DAC96k 0x01C 283

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#define N12_ADC48k_DAC48k 0x000 284

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#define N12_ADC32k_DAC32k 0x018 285

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#define N12_ADC8k_DAC8k 0x00C 286 287 /* normal mode - MCLK = 11.2896MHz */ 288

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#define N11_ADC88k2_DAC88k2 0x03C 289

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#define N11_ADC44k1_DAC44k1 0x020 290

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#define N11_ADC8k021_DAC8k021 0x02C 291 292 293

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#define CLKMOD 0x001 /* clock mode select; 0 = normal, 1 = USB */ 294

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#define CLKMOD_normal 0x000 295

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#define CLKMOD_USB CLKMOD /* FITkit has 12MHz clock -> USB mode */ 296 297 /* digital interface activation (9 bits) 298 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 299 * | X | RES | RES | X | X | X | X | X | ACT | 300 * default 301 * 0 0 0 0 0 0 0 0 0 302 */ 303 //#define DIARES 0x1FE /* reserved bits */ 304

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#define ACT 0x001 /* activate interface; 0 = inactive, 1 = active */ 305

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#define ACT_on ACT 306

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#define ACT_off 0x000 307 308 /* reset register (9 bits) 309 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 310 * | RES | RES | RES | RES | RES | RES | RES | RES | RES | 311 * default 312 * 0 0 0 0 0 0 0 0 0 313 */ 314

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#define RES 0x1FF /* write 000000000 to this register triggers reset */ 315 316 /******************************************************************************* 317 * function sends codec configuration data via SPI 318 ******************************************************************************/ 319 void codec_SPI_write(unsigned int addr, unsigned int data); 320 321

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#endif /* _AUDIO_CODEC_H_ */ 322
Zobrazeno: 162256x Naposledy: 22.1.2018 20:47:01