SVN Repository / Prohlížení

vga_config.vhd

   1  -- vga_config.vhd: VGA constants & definitions
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Ladislav Capka <xcapka01 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  
  48  package vga_controller_cfg is
  49     type modes is (rUnknown,
  50                    r640x480x60, r640x480x66, --r640x480x72, r640x480x75,
  51                    --r720x400x70, r720x350x70,
  52                    --r800x600x56, r800x600x60,
  53                    r800x600x72);
  54  
  55     type vga_hfsm_state is (hstDisabled, hstPrepare, hstRequestOnly, hstDraw,
  56                         hstDrawOnly, hstWaitSync, hstSync, hstWaitPeriod);
  57     type vga_vfsm_state is (vstPrepare, vstDraw, vstWaitSync, vstSync, vstWaitPeriod);
  58  
  59     subtype resolution is std_logic_vector(11 downto 0);
  60     subtype color is integer range 0 to 7;
  61  
  62     procedure setrgb(signal r, g, b : out std_logic_vector(2 downto 0); constant val_r, val_g, val_b : color);
  63     procedure setmode(constant mode : modes; signal settings : out std_logic_vector(60 downto 0));
  64  end vga_controller_cfg;
  65  
  66  package body vga_controller_cfg is
  67     procedure setrgb(signal r, g, b : out std_logic_vector(2 downto 0); constant val_r, val_g, val_b : color) is
  68     begin
  69        r <= conv_std_logic_vector(val_r, 3);
  70        g <= conv_std_logic_vector(val_g, 3);
  71        b <= conv_std_logic_vector(val_b, 3);
  72     end setrgb;
  73  
  74     procedure setmode(constant mode : modes; signal settings : out std_logic_vector(60 downto 0)) is
  75     begin
  76         case mode is
  77             when r640x480x60 =>
  78                 settings(60 downto 49) <= conv_std_logic_vector(640 -1, 12); -- h_pixels    12 bit (0-4095)
  79                 settings(48 downto 37) <= conv_std_logic_vector(480 -0, 12); -- v_lines     12 bit (0-4095)
  80                 settings(36 downto 30) <= conv_std_logic_vector(16  -1,  7); -- h_syncstart  7 bit (0-127)
  81                 settings(29 downto 23) <= conv_std_logic_vector(96  -1,  7); -- h_syncend    7 bit (0-127)
  82                 settings(22 downto 16) <= conv_std_logic_vector(48  -1,  7); -- h_period     7 bit (0-127)
  83                 settings(15 downto 10) <= conv_std_logic_vector(10  -0,  6); -- v_syncstart  6 bit (0-63)
  84                 settings(9 downto 6)   <= conv_std_logic_vector(2   -0,  4); -- v_syncend    4 bit (0-63)
  85                 settings(5 downto 0)   <= conv_std_logic_vector(33  -0,  6); -- v_period     6 bit (0-63)
  86  
  87             when r640x480x66 =>
  88                 settings(60 downto 49) <= conv_std_logic_vector(640 -1, 12);
  89                 settings(48 downto 37) <= conv_std_logic_vector(480 -0, 12);
  90                 settings(36 downto 30) <= conv_std_logic_vector(61  -1,  7);
  91                 settings(29 downto 23) <= conv_std_logic_vector(64  -1,  7);
  92                 settings(22 downto 16) <= conv_std_logic_vector(99  -1,  7);
  93                 settings(15 downto 10) <= conv_std_logic_vector(1   -0,  6);
  94                 settings(9 downto 6)   <= conv_std_logic_vector(3   -0,  4);
  95                 settings(5 downto 0)   <= conv_std_logic_vector(41  -0,  6);
  96  
  97             when r800x600x72 =>
  98                 settings(60 downto 49) <= conv_std_logic_vector(800 -1, 12);
  99                 settings(48 downto 37) <= conv_std_logic_vector(600 -0, 12);
 100                 settings(36 downto 30) <= conv_std_logic_vector(53  -1,  7);
 101                 settings(29 downto 23) <= conv_std_logic_vector(120 -1,  7);
 102                 settings(22 downto 16) <= conv_std_logic_vector(67  -1,  7);
 103                 settings(15 downto 10) <= conv_std_logic_vector(35  -0,  6);
 104                 settings(9 downto 6)   <= conv_std_logic_vector(6   -0,  4);
 105                 settings(5 downto 0)   <= conv_std_logic_vector(25  -0,  6);
 106  
 107             when others =>
 108                 settings(60 downto 49) <= conv_std_logic_vector(0, 12);
 109                 settings(48 downto 37) <= conv_std_logic_vector(0, 12);
 110                 settings(36 downto 30) <= conv_std_logic_vector(0, 7);
 111                 settings(29 downto 23) <= conv_std_logic_vector(0, 7);
 112                 settings(22 downto 16) <= conv_std_logic_vector(0, 7);
 113                 settings(15 downto 10) <= conv_std_logic_vector(0, 6);
 114                 settings(9 downto 6)   <= conv_std_logic_vector(0, 4);
 115                 settings(5 downto 0)   <= conv_std_logic_vector(0, 6);
 116         end case;
 117     end setmode;
 118  end vga_controller_cfg;
 119