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spi_reg.vhd

   1  -- spi_reg.vhd:
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  library ieee;
  44  use ieee.std_logic_1164.all;
  45  use ieee.std_logic_arith.all;
  46  
  47  package spi_cfg is
  48     type port_dir is (PORT_IN, PORT_OUT);
  49  end spi_cfg;
  50  
  51  library IEEE;
  52  use ieee.std_logic_1164.all;
  53  use ieee.std_logic_arith.all;
  54  use ieee.std_logic_unsigned.all;
  55  --use work.spi_cfg.all;
  56  
  57  entity SPI_reg is
  58     generic (
  59        ADDR_WIDTH : integer := 8;
  60        DATA_WIDTH : integer := 8;
  61        BASE_ADDR  : integer := 16#10#;
  62        BYPASS     : boolean := false
  63  --      DIRECTION  : port_dir := PORT_OUT
  64     );
  65     port (
  66        -- Synchronizace
  67        CLK      : in  std_logic;
  68  
  69        -- Rozhrani SPI (z SPI_control)
  70        CS       : in  std_logic;
  71        DO       : in  std_logic;
  72        DO_VLD   : in  std_logic;
  73        DI       : out std_logic;
  74        DI_REQ   : in  std_logic;
  75  
  76        --Datove rozhrani
  77        DATA_IN  : in  std_logic_vector (DATA_WIDTH-1 downto 0);
  78        DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0)
  79     );
  80  end SPI_reg;
  81  
  82  
  83  architecture beh of SPI_reg is
  84  
  85     component SPI_adc
  86        generic (
  87           DELAY      : integer := 1;
  88           ADDR_WIDTH : integer := ADDR_WIDTH;
  89           DATA_WIDTH : integer := DATA_WIDTH;
  90           ADDR_OUT_WIDTH : integer := 1;
  91           BASE_ADDR  : integer := BASE_ADDR
  92        );
  93        port (
  94           CLK      : in  std_logic;
  95  
  96           CS       : in  std_logic;
  97           DO       : in  std_logic;
  98           DO_VLD   : in  std_logic;
  99           DI       : out std_logic;
 100           DI_REQ   : in  std_logic;
 101  
 102           ADDR     : out std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
 103           DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
 104           DATA_IN  : in  std_logic_vector (DATA_WIDTH-1 downto 0);
 105  
 106           WRITE_EN : out std_logic;
 107           READ_EN  : out std_logic
 108        );
 109     end component;
 110  
 111     signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
 112     signal spi_data_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
 113     signal spi_data_in  : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
 114     signal spi_we, spi_re : std_logic;
 115  
 116  begin
 117  
 118     -- SPI_ADC pro pristup do instrukcni pameti
 119     spi_cpu_ram: SPI_adc
 120        port map (
 121           CLK      => CLK,
 122  
 123           CS       => CS,
 124           DO       => DO,
 125           DO_VLD   => DO_VLD,
 126           DI       => DI,
 127           DI_REQ   => DI_REQ,
 128  
 129           ADDR     => open,
 130           DATA_OUT => spi_data_out,
 131           DATA_IN  => spi_data_in,
 132  
 133           WRITE_EN => spi_we,
 134           READ_EN  => spi_re
 135        );
 136  
 137        process (CLK)
 138        begin
 139           if (CLK'event) and (CLK = '1') then
 140  
 141              if (spi_re = '1') then
 142                 if (BYPASS) then
 143                    spi_data_in <= data_reg;
 144                 else
 145                    spi_data_in <= DATA_IN;
 146                 end if;
 147              end if;
 148  
 149              if (spi_we = '1') then
 150                 data_reg <= spi_data_out;
 151              end if;
 152  
 153           end if;
 154        end process;
 155  
 156        DATA_OUT <= (others=>'Z') when BYPASS else
 157                    data_reg;
 158  
 159  end architecture;
 160