Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / fpga / ctrls / spi /

spi_ctrl.vhd

   1  -- spi_ctrl.vhd : SPI Controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  library IEEE;
  44  use IEEE.STD_LOGIC_1164.ALL;
  45  use IEEE.STD_LOGIC_ARITH.ALL;
  46  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  47  
  48  -- SYNTH-ISE: slices=4, slicesFF=5, 4luts=7
  49  entity SPI_ctrl is
  50     port (
  51        -- Reset a synchronizace
  52        RST     : in   std_logic;
  53        CLK     : in   std_logic;
  54  
  55        -- Rozhrani SPI (z master MCU)
  56        SPI_CLK : in   std_logic;
  57        SPI_CS  : in   std_logic;
  58        SPI_MOSI: in   std_logic;
  59        SPI_MISO: out  std_logic;
  60  
  61        -- Interni rozhrani
  62        DI      : in   std_logic;   -- Serial data in (MISO)
  63        DI_REQ  : out  std_logic;   -- DI request
  64        DO      : out  std_logic;   -- Serial data out (MOSI)
  65        DO_VLD  : out  std_logic;   -- DO valid
  66        CS      : out  std_logic    -- internal SPI active
  67     );
  68  end SPI_ctrl;
  69  
  70  
  71  
  72  architecture Arch_SPI_ctrl2 of SPI_ctrl is
  73  
  74  type    FSMstate is (SInit, SRcv1, SRcv2, SRcv3, SActive, SNActive);
  75  signal  pstate    : FSMstate; -- actual state
  76  signal  nstate    : FSMstate; -- next state
  77  
  78  signal  dovld     : std_logic;
  79  signal  devsel    : std_logic;
  80  signal  spi_clk_1 : std_logic;
  81  signal  spi_clk_2 : std_logic;
  82  
  83  begin
  84  
  85     -- FSM
  86     process (SPI_CS, CLK)
  87     begin
  88        if (SPI_CS = '1') then
  89           pstate <= SInit;
  90        elsif (CLK'event) and (CLK='1') then
  91           if (dovld = '1') then
  92              pstate <= nstate;
  93           end if;
  94        end if;
  95     end process;
  96  
  97     process (pstate, SPI_MOSI)
  98     begin
  99        nstate <= SInit;
 100        devsel <= '0';
 101        case pstate is
 102           when SInit =>
 103              nstate <= SNActive;
 104              if (SPI_MOSI = '0') then
 105                 nstate <= SRcv1;
 106              end if;
 107  
 108           -- first bit received and was 1
 109           when SRcv1 =>
 110              nstate <= SNActive;
 111              if (SPI_MOSI = '0') then
 112                 nstate <= SRcv2;
 113              end if;
 114  
 115          -- second bit received and was 1
 116          when SRcv2 =>
 117              nstate <= SNActive;
 118              if (SPI_MOSI = '0') then
 119                 nstate <= SRcv3;
 120              end if;
 121  
 122          -- third bit received and was 1
 123          when SRcv3 =>
 124              nstate <= SNActive;
 125              if (SPI_MOSI = '1') then
 126                 nstate <= SActive;
 127              end if;
 128  
 129          -- first four bits were 0001
 130          when SActive =>
 131              nstate <= SActive;
 132              devsel <= '1';
 133  
 134          when SNActive =>
 135              nstate <= SNActive;
 136  
 137       end case;
 138     end process;
 139  
 140     -- SPI_CLK edge detector
 141     process (RST, CLK)
 142     begin
 143        if (RST = '1') then
 144           spi_clk_1 <= '1'; --SPI_CLK inactive state is '1'
 145           spi_clk_2 <= '1';
 146        elsif (CLK'event) and (CLK = '1') then
 147           spi_clk_1 <= SPI_CLK;
 148           spi_clk_2 <= spi_clk_1;
 149        end if;
 150     end process;
 151  
 152     CS <= not SPI_CS when (devsel='1') else '0';
 153  
 154     -- signal DI must be valid during the whole SCK period,
 155     -- typically meet because SPI decoder contains data shift register
 156     SPI_MISO <= DI when (devsel='1') else 'Z';
 157     DO <= SPI_MOSI;
 158  
 159     dovld <= spi_clk_1 and (not spi_clk_2);   -- rising edge
 160     DI_REQ <= (not spi_clk_1) and  spi_clk_2;  -- falling edge
 161     DO_VLD <= dovld;
 162  
 163  end Arch_SPI_ctrl2;
 164  
 165  
Zobrazeno: 679789x Naposledy: 28.6.2022 20:45:13