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Aktuální adresář: FITkit / trunk / fpga / ctrls / spi /

spi_adc_entity.vhd

   1  -- spi_adc_entity.vhd : SPI Decoder Entity
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  
  47  entity SPI_adc is
  48     generic (
  49        DELAY      : integer := 0;  -- zpozdeni (pocet taktu) mezi READ_EN a vystavenim dat na DATA_IN
  50        ADDR_WIDTH : integer := 8;  -- sirka adresy
  51        DATA_WIDTH : integer := 8;  -- sirka dat
  52        ADDR_OUT_WIDTH : integer := 4; -- sirka adresy na vystupu (0 <= ADR_OUT_WIDTH <= ADDR_WIDTH)
  53        BASE_ADDR  : integer := 16#10# -- adresovy prostor 10-1F
  54     );
  55     port (
  56        -- Synchronizace
  57        CLK      : in  std_logic;
  58  
  59        -- Rozhrani SPI (z SPI_control)
  60        CS       : in  std_logic;
  61        DO       : in  std_logic;
  62        DO_VLD   : in  std_logic;
  63        DI       : out std_logic;
  64        DI_REQ   : in  std_logic;
  65  
  66        --Datove rozhrani
  67        ADDR     : out  std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
  68        DATA_OUT : out  std_logic_vector (DATA_WIDTH-1 downto 0);
  69        DATA_IN  : in   std_logic_vector (DATA_WIDTH-1 downto 0);
  70  
  71        WRITE_EN : out  std_logic; --write to FPGA through DATA_OUT
  72        READ_EN  : out  std_logic  --read from FPGA through DATA_IN
  73     );
  74  end SPI_adc;
  75  
  76  
Zobrazeno: 679749x Naposledy: 28.6.2022 20:02:31