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serial_clkgen.vhd

   1  -- serial_clkgen.vhd : Baudrate generator
   2  -- Copyright (C) 2007 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek (xvasic11 AT stud.fit.vutbr.cz)
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.std_logic_1164.ALL;
  46  use IEEE.std_logic_ARITH.ALL;
  47  use IEEE.std_logic_UNSIGNED.ALL;
  48  use work.serial_cfg.ALL;
  49  
  50  entity serial_gen is
  51     generic (
  52        SPEED     : serial_speed := s921600Bd; -- Serial speed
  53        FREQMULT  : positive := 1 -- divisor 8/FREQMULT is used for 921 600 Bd (SMCLK/8 = 7.3728MHz/8)
  54     );
  55     port (
  56        CLK         : in  std_logic;
  57        RESET       : in  std_logic;
  58        EN          : in  std_logic;
  59  
  60        OUTPUT      : out std_logic
  61     );
  62  end serial_gen;
  63  
  64  architecture behavioral of serial_gen is
  65     --maximal value of counter
  66     constant CNT_MAX  : integer := clkdiv(SPEED, FREQMULT);
  67     --minimal number of bits to achieve CNT_MAX
  68     constant CNT_BITS : integer := log2(CNT_MAX-1);
  69  
  70     signal cnt_reg : std_logic_vector(CNT_BITS-1 downto 0) := (others => '0');
  71     signal cnt_cmp : std_logic;
  72  begin
  73  
  74     -- Counter
  75     process (RESET, CLK)
  76     begin
  77        if (RESET = '1') then
  78           cnt_reg <= (others => '0');
  79        elsif (CLK'event) and (CLK = '1') then
  80           if (EN = '1') then
  81              if (cnt_cmp = '1') then
  82                 cnt_reg <= (others => '0');
  83              else
  84                 cnt_reg <= cnt_reg + 1;
  85              end if;
  86           end if;
  87        end if;
  88     end process;
  89  
  90     --Comparator
  91     cnt_cmp <= '1' when (CNT_MAX = 1) or (cnt_reg = conv_std_logic_vector(CNT_MAX-1, CNT_BITS)) else '0';
  92  
  93     --Output enable signal
  94     OUTPUT <= cnt_cmp and EN;
  95  
  96  end behavioral;
  97  
Zobrazeno: 679750x Naposledy: 28.6.2022 20:03:12