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Aktuální adresář: FITkit / trunk / fpga / ctrls / serial /

serial.vhd

   1  -- serial.vhd : Serial transceiver
   2  -- Copyright (C) 2007 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek (xvasic11 AT stud.fit.vutbr.cz)
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.STD_LOGIC_1164.ALL;
  46  use IEEE.STD_LOGIC_ARITH.ALL;
  47  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  48  use work.serial_cfg.all;
  49  
  50  entity serial_transceiver is
  51     generic (
  52        SPEED     : serial_speed   := s460800Bd;
  53        DATAWIDTH : serial_databit := 8;
  54        STOPBITS  : serial_stopbit := 1;
  55        PARITY    : serial_parity  := sParityEven
  56     );
  57     port (
  58        CLK      : in std_logic;
  59        RESET    : in std_logic;
  60  
  61        DATA_IN  : in std_logic_vector(DATAWIDTH-1 downto 0);
  62        WRITE_EN : in std_logic;
  63  
  64        DATA_OUT : out std_logic_vector(DATAWIDTH-1 downto 0);
  65        DATA_VLD : out std_logic;
  66  
  67        BUSY     : out std_logic;
  68        ERR      : out std_logic;
  69        ERR_RST  : in  std_logic;
  70  
  71        -- RS232
  72        RXD      : in  std_logic;
  73        TXD      : out std_logic;
  74        RTS      : in  std_logic;
  75        CTS      : out std_logic
  76     );
  77  end serial_transceiver;
  78  
  79  
  80  architecture struct of serial_transceiver is
  81  
  82     component serial_transmitter
  83        generic (
  84           SPEED     : serial_speed := SPEED;
  85           DATAWIDTH : serial_databit := DATAWIDTH;
  86           STOPBITS  : serial_stopbit := STOPBITS;
  87           PARITY    : serial_parity := PARITY
  88        );
  89        port (
  90           -- Common interface
  91           CLK      : in std_logic;
  92           RESET    : in std_logic;
  93  
  94           DATA_IN  : in std_logic_vector(DATAWIDTH-1 downto 0);
  95           WRITE_EN : in std_logic;
  96  
  97           BUSY     : out std_logic;
  98  
  99           -- Serial interface
 100           TXD      : out std_logic
 101        );
 102     end component;
 103  
 104     component serial_receiver
 105        generic (
 106           SPEED     : serial_speed := SPEED;
 107           DATAWIDTH : serial_databit := DATAWIDTH;
 108           STOPBITS  : serial_stopbit := STOPBITS;
 109           PARITY    : serial_parity := PARITY
 110        );
 111        port (
 112           CLK      : in std_logic;
 113           RESET    : in std_logic;
 114  
 115           DATA_OUT : out std_logic_vector(DATAWIDTH-1 downto 0);
 116           DATA_VLD : out std_logic;
 117  
 118           BUSY     : out std_logic;
 119           ERR      : out std_logic;
 120           ERR_RST  : in  std_logic;
 121  
 122           -- Serial interface
 123           RXD      : in  std_logic
 124        );
 125     end component;
 126  
 127  begin
 128     CTS <= '1';
 129  
 130     rx: serial_receiver
 131        generic map (
 132           SPEED => SPEED,
 133           DATAWIDTH => DATAWIDTH,
 134           STOPBITS => STOPBITS,
 135           PARITY => PARITY
 136        )
 137        port map (
 138           CLK => CLK,
 139           RESET => RESET,
 140           DATA_OUT => DATA_OUT,
 141           DATA_VLD => DATA_VLD,
 142           BUSY => open,
 143           ERR => ERR,
 144           ERR_RST => ERR_RST,
 145           RXD => RXD
 146        );
 147  
 148     tx: serial_transmitter
 149        generic map (
 150           SPEED => SPEED,
 151           DATAWIDTH => DATAWIDTH,
 152           STOPBITS => STOPBITS,
 153           PARITY => PARITY
 154        )
 155        port map (
 156           CLK => CLK,
 157           RESET => RESET,
 158           DATA_IN => DATA_IN,
 159           WRITE_EN => WRITE_EN,
 160           BUSY => BUSY,
 161           TXD => TXD
 162        );
 163  
 164  end struct;
 165  
 166  
Zobrazeno: 679780x Naposledy: 28.6.2022 20:35:44