SVN Repository / Prohlížení

majority.vhd

   1  -- majority.vhd : Majority of five inputs
   2  -- Copyright (C) 2007 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek (xvasic11 AT stud.fit.vutbr.cz)
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.STD_LOGIC_1164.ALL;
  46  use IEEE.STD_LOGIC_ARITH.ALL;
  47  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  48  
  49  -- pragma translate_off
  50  library unisim;
  51  use unisim.vcomponents.ALL;
  52  -- pragma translate_on
  53  
  54  entity majority_five is
  55     port (
  56        D : in  std_logic_vector(4 downto 0);
  57        Q : out std_logic
  58     );
  59  end majority_five;
  60  
  61  
  62  architecture struct of majority_five is
  63  
  64     component ROM32x1
  65        generic (
  66           INIT : bit_vector := X"FEE8E880"
  67        );
  68        port (
  69           O  : out STD_ULOGIC;
  70           A0 : in STD_ULOGIC;
  71           A1 : in STD_ULOGIC;
  72           A2 : in STD_ULOGIC;
  73           A3 : in STD_ULOGIC;
  74           A4 : in STD_ULOGIC
  75        );
  76     end component;
  77  
  78     attribute INIT : bit_vector;
  79     attribute INIT of bit_majority : label is X"FEE8E880";
  80  
  81  begin
  82     -- Truth Table
  83     --  I0 I1 I2 I3 I4   O
  84     --  0  0  0  0  0    0    (bit 0)
  85     --  0  0  0  0  1    0
  86     --  0  0  0  1  0    0
  87     --  0  0  0  1  1    0
  88     --  0  0  1  0  0    0
  89     --  0  0  1  0  1    0
  90     --  0  0  1  1  0    0
  91     --  0  0  1  1  1    1    (bit 7)
  92     --  ==================
  93     --  0  1  0  0  0    0    (bit 0)
  94     --  0  1  0  0  1    0
  95     --  0  1  0  1  0    0
  96     --  0  1  0  1  1    1
  97     --  0  1  1  0  0    0
  98     --  0  1  1  0  1    1
  99     --  0  1  1  1  0    1
 100     --  0  1  1  1  1    1    (bit 7)
 101     --  ==================
 102     --  1  0  0  0  0    0    (bit 0)
 103     --  1  0  0  0  1    0
 104     --  1  0  0  1  0    0
 105     --  1  0  0  1  1    1
 106     --  1  0  1  0  0    0
 107     --  1  0  1  0  1    1
 108     --  1  0  1  1  0    1
 109     --  1  0  1  1  1    1    (bit 7)
 110     --  ==================
 111     --  1  1  0  0  0    0    (bit 0)
 112     --  1  1  0  0  1    1
 113     --  1  1  0  1  0    1
 114     --  1  1  0  1  1    1
 115     --  1  1  1  0  0    1
 116     --  1  1  1  0  1    1
 117     --  1  1  1  1  0    1
 118     --  1  1  1  1  1    1    (bit 7)
 119  
 120     bit_majority : ROM32X1
 121        generic map (
 122           INIT => X"FEE8E880"
 123        )
 124        port map (
 125           O =>  Q,
 126           A0 => D(0),
 127           A1 => D(1),
 128           A2 => D(2),
 129           A3 => D(3),
 130           A4 => D(4)
 131        );
 132  
 133  end struct;
 134  
 135