FITkitSVN Repository / Prohlížení
Aktuální adresář: FITkit / trunk / fpga / ctrls / sdram /
sdram_raw_ctrl.vhd
1 -- sdram.vhd: SDRAM base controller 2 -- Copyright (C) 2006 Brno University of Technology, 3 -- Faculty of Information Technology 4 -- Author(s): Ladislav Capka <xcapka01 AT stud.fit.vutbr.cz> 5 -- 6 -- LICENSE TERMS 7 -- 8 -- Redistribution and use in source and binary forms, with or without 9 -- modification, are permitted provided that the following conditions 10 -- are met: 11 -- 1. Redistributions of source code must retain the above copyright 12 -- notice, this list of conditions and the following disclaimer. 13 -- 2. Redistributions in binary form must reproduce the above copyright 14 -- notice, this list of conditions and the following disclaimer in 15 -- the documentation and/or other materials provided with the 16 -- distribution. 17 -- 3. All advertising materials mentioning features or use of this software 18 -- or firmware must display the following acknowledgement: 19 -- 20 -- This product includes software developed by the University of 21 -- Technology, Faculty of Information Technology, Brno and its 22 -- contributors. 23 -- 24 -- 4. Neither the name of the Company nor the names of its contributors 25 -- may be used to endorse or promote products derived from this 26 -- software without specific prior written permission. 27 -- 28 -- This software or firmware is provided ``as is'', and any express or implied 29 -- warranties, including, but not limited to, the implied warranties of 30 -- merchantability and fitness for a particular purpose are disclaimed. 31 -- In no event shall the company or contributors be liable for any 32 -- direct, indirect, incidental, special, exemplary, or consequential 33 -- damages (including, but not limited to, procurement of substitute 34 -- goods or services; loss of use, data, or profits; or business 35 -- interruption) however caused and on any theory of liability, whether 36 -- in contract, strict liability, or tort (including negligence or 37 -- otherwise) arising in any way out of the use of this software, even 38 -- if advised of the possibility of such damage. 39 -- 40 -- $Id$ 41 -- 42 -- 43 44 library ieee; 45 use ieee.std_logic_1164.all; 46 use ieee.std_logic_arith.all; 47 use ieee.std_logic_unsigned.all; 48 use work.sdram_controller_cfg.all; 49 50 -- SYNTH-ISE-9.2: slices=127, slicesFF=151, 4luts=169 51 entity sdram_raw_controller is 52 generic ( 53 -- Generovani prikazu refresh radicem automaticky 54 GEN_AUTO_REFRESH : boolean := true; 55 OPTIMIZE_REFRESH : sdram_optimize := oAlone -- deprecated 56 ); 57 port ( 58 -- Clock, reset, ... 59 CLK : in std_logic; 60 RST : in std_logic; 61 ENABLE : in std_logic; 62 BUSY : out std_logic; 63 64 -- Address/data 65 ADDR_ROW : in std_logic_vector(11 downto 0); 66 ADDR_COLUMN : in std_logic_vector(8 downto 0); 67 BANK : in std_logic_vector(1 downto 0); 68 DATA_IN : in std_logic_vector(7 downto 0); 69 DATA_OUT : out std_logic_vector(7 downto 0); 70 DATA_VLD : out std_logic; -- Output data valid 71 72 -- Command signal/set 73 CMD : in sdram_func; 74 CMD_WE : in std_logic; 75 76 -- Signals to SDRAM 77 RAM_A : out std_logic_vector(13 downto 0); 78 RAM_D : inout std_logic_vector(7 downto 0); 79 RAM_DQM : out std_logic; 80 RAM_CS : out std_logic; 81 RAM_RAS : out std_logic; 82 RAM_CAS : out std_logic; 83 RAM_WE : out std_logic; 84 RAM_CLK : out std_logic; 85 RAM_CKE : out std_logic 86 ); 87 end sdram_raw_controller; 88 89 architecture arch_sdram_raw_controller of sdram_raw_controller is 90 91 type tstate is (stReset, 92 stIdle, 93 stCmdWait, 94 stCmdLMR, 95 stCmdSelect, 96 stCmdRead, 97 stCmdWrite, 98 stCmdCharge, 99 stCmdRefresh); 100 101 type tistate is (csi_Begin, 102 csi_Idle, 103 csi_Chg, 104 csi_Ref1, 105 csi_Ref2, 106 csi_Ref3, 107 csi_Ref4, 108 csi_Ref5, 109 csi_Ref6, 110 csi_Ref7, 111 csi_LMR, 112 csi_End); 113 114 type tcmd_len is (t1clk, t2clk, t3clk, t7clk); 115 116 -- Init FSM states 117 signal cstate_init : tistate; 118 signal nstate_init : tistate; 119 120 -- RAM command (RCKE RDQM CS RAS CAS WE) 121 signal ram_cmd : std_logic_vector(5 downto 0); 122 signal ram_a_sel : std_logic_vector(1 downto 0); 123 124 -- Controler state (current/next/future) 125 signal cstate : tstate; 126 signal nstate : tstate; 127 128 signal iready : std_logic; 129 130 -- State timing counter 131 signal cnt : std_logic_vector(2 downto 0); 132 signal cnt_set : std_logic_vector(2 downto 0); 133 signal cnt_mx : std_logic; 134 signal cnt_load : std_logic; 135 signal cnt_value : tcmd_len; 136 137 -- RAM controller command 138 signal cmd_fifo_reg : sdram_func; 139 signal cmd_loaded : std_logic; 140 signal cmd_ld_xor1 : std_logic; 141 signal cmd_ld_xor2 : std_logic; 142 signal cmd_ld_en : std_logic; 143 signal cmd_as_state : tstate; 144 145 -- Fifo row/col/bank, data 146 signal row_fifo_reg : std_logic_vector(11 downto 0); 147 signal col_fifo_reg : std_logic_vector(8 downto 0); 148 signal bnk_fifo_reg : std_logic_vector(1 downto 0); 149 signal din_fifo_reg : std_logic_vector(7 downto 0); 150 151 signal dout_reg : std_logic_vector(7 downto 0); 152 153 signal dout_ready : std_logic; 154 signal din_ready : std_logic; 155 156 signal row_bus_reg : std_logic_vector(11 downto 0); 157 signal column_bus_reg : std_logic_vector(8 downto 0); 158 signal bank_bus_reg : std_logic_vector(1 downto 0); 159 signal data_bus_reg : std_logic_vector(7 downto 0); 160 161 -- Refresh request 162 signal ref_mx : std_logic; 163 signal ref_cnt : std_logic_vector(9 downto 0); 164 165 -- Read latency 2 shift (latency 3 need 4 bit shift) 166 signal lat_sh : std_logic_vector(2 downto 0) := "000"; 167 168 -- Additional FSM state logic 169 signal cs_cc : std_logic; 170 signal cs_cf : std_logic; 171 signal cs_cs : std_logic; 172 signal cs_cr : std_logic; 173 signal cs_cw : std_logic; 174 175 -- Generic to logic translation 176 signal GENERIC_GAF : std_logic; 177 178 -- Init logic 179 signal init_p0 : std_logic; 180 signal init_p1 : std_logic; 181 signal init_p2 : std_logic; 182 signal inited : std_logic; 183 184 -- External operation 185 signal cf_crw : std_logic; 186 signal cf_cw : std_logic; 187 signal cf_cr : std_logic; 188 signal cf_cf : std_logic; 189 190 -- Active bank's row 191 signal actrows : std_logic_vector(51 downto 0); 192 signal actrow : std_logic_vector(12 downto 0); 193 signal arow : std_logic_vector(12 downto 0); 194 signal resel_mx : std_logic; 195 signal bnk1 : std_logic; 196 signal bnk2 : std_logic; 197 signal bnk3 : std_logic; 198 signal bnk4 : std_logic; 199 200 -- State signals/State regs 201 signal cha : std_logic; 202 signal chg : std_logic; 203 signal chg_reg : std_logic; 204 signal ref : std_logic; 205 signal ref_reg : std_logic; 206 signal sel : std_logic; 207 signal sel_reg : std_logic; 208 signal fff : std_logic; 209 signal fff_reg : std_logic; 210 signal out_ld : std_logic; 211 signal out_reg : std_logic; 212 213 signal waw : std_logic; 214 signal rar : std_logic; 215 signal raw : std_logic; 216 217 begin 218 219 -- Generic GEN_AUTO_REFRESH true/false -> 0/1 220 GENERIC_GAF <= '1' when GEN_AUTO_REFRESH = true else '0'; 221 222 RAM_CLK <= CLK; 223 RAM_CKE <= ram_cmd(5); 224 RAM_DQM <= ram_cmd(4); 225 RAM_CS <= ram_cmd(3); 226 RAM_RAS <= ram_cmd(2); 227 RAM_CAS <= ram_cmd(1); 228 RAM_WE <= ram_cmd(0); 229 BUSY <= not iready; 230 DATA_VLD <= lat_sh(2); -- Read data valid after latency logic 231 DATA_OUT <= dout_reg; 232 233 -- Set data for RAM (RD) 234 RAM_D <= data_bus_reg when din_ready = '1' else (others => 'Z'); 235 236 -- Busy logic 237 iready <= inited and not fff_reg; 238 239 -- Idle count logic 240 cnt_mx <= cnt(0) and cnt(1) and cnt(2); -- cnt=7 241 cnt_set <= "001" when (cnt_value = t7clk) else 242 "101" when (cnt_value = t3clk) else 243 "110" when (cnt_value = t2clk) else 244 "111" when (cnt_value = t1clk) else 245 "111"; 246 247 -- Cmd load logic 248 cmd_loaded <= cmd_ld_xor1 xor cmd_ld_xor2; 249 cmd_ld_en <= CMD_WE and iready and ENABLE; 250 251 -- Bank selection 252 bnk1 <= chg_reg or sel_reg when bnk_fifo_reg = "00" else ref_reg; 253 bnk2 <= chg_reg or sel_reg when bnk_fifo_reg = "01" else ref_reg; 254 bnk3 <= chg_reg or sel_reg when bnk_fifo_reg = "10" else ref_reg; 255 bnk4 <= chg_reg or sel_reg when bnk_fifo_reg = "11" else ref_reg; 256 257 -- Row selected in next command mx 258 actrow <= actrows(12 downto 0) when bnk_fifo_reg = "00" 259 else actrows(25 downto 13) when bnk_fifo_reg = "01" 260 else actrows(38 downto 26) when bnk_fifo_reg = "10" 261 else actrows(51 downto 39) when bnk_fifo_reg = "11"; 262 263 -- Need row reselection? 264 resel_mx <= '1' when actrow(11 downto 0) /= row_fifo_reg else '0'; 265 266 ----------------------------------------------------------------------------- 267 -- Autorefresh gen counter limit (10 bit): 1100000000 = 15.360 us (50 MHz) 268 ref_mx <= (ref_cnt(9) and ref_cnt(8) and GENERIC_GAF); 269 270 ----------------------------------------------------------------------------- 271 -- Input command logic 272 cmd_as_state <= stCmdRead when cmd_fifo_reg = fRead 273 else stCmdWrite when cmd_fifo_reg = fWrite 274 else stCmdRefresh when cmd_fifo_reg = fRefresh 275 else stCmdWait; 276 277 ----------------------------------------------------------------------------- 278 -- Next (FIFO) opration logic 279 cf_cr <= '1' when cmd_fifo_reg = fRead else '0'; 280 cf_cw <= '1' when cmd_fifo_reg = fWrite else '0'; 281 cf_cf <= '1' when cmd_fifo_reg = fRefresh else '0'; 282 cf_crw <= cf_cr or cf_cw; 283 284 ----------------------------------------------------------------------------- 285 -- State flag logic 286 287 -- Charge all rows when need refresh 288 cha <= ((cf_cf and cmd_loaded) or (ref_mx and not fff_reg)) and 289 (actrows(12) or actrows(25) or actrows(38) or actrows(51)); 290 291 -- Charge if ram will be refreshed OR loaded RD/WR & INCORRECT ROW SELECTED 292 chg <= cha or (cf_crw and resel_mx and cmd_loaded and actrow(12)); 293 294 -- Refresh flag 295 ref <= (ref_mx and not fff_reg) or (cf_cf and cmd_loaded); 296 297 -- Select if loaded RD/WR and reselect/nothing selected 298 sel <= cf_crw and (resel_mx or not actrow(12)) and cmd_loaded; 299 300 -- Fifo full if chg OR sel flag set OR 301 -- (not prepare command finished AND operation in FIFO can't be optimized 302 -- by read-after-read, write-after-write or read-after-write techniques) 303 --fff <= chg or sel or (not rar and not waw and not raw and cmd_loaded) or not cnt_mx; 304 fff <= chg or sel or (not rar and not waw and not raw and cmd_loaded) or (not cnt_mx and cmd_loaded); 305 306 -- Optimize flags (read-after-read, write-after-write, read-after-write) 307 -- WARN: when R/W state was finished and IDLE now take latency time, flags aren't set 308 rar <= cs_cr and cf_cr and not resel_mx and cmd_loaded; 309 waw <= cs_cw and cf_cw and not resel_mx and cmd_loaded; 310 raw <= cs_cw and cf_cr and not resel_mx and cmd_loaded; 311 312 out_ld <= (out_reg and not fff_reg) or rar or waw or raw; 313 314 -- row is unselected when REFRESH flasg set 315 arow <= (not ref_reg) & row_bus_reg; --'1' & row_bus_reg when ref_reg = '0' else (others => '0'); 316 317 ----------------------------------------------------------------------------- 318 -- State flag registers 319 state_registers: process(RST, CLK) 320 begin 321 if RST = '1' then 322 chg_reg <= '0'; 323 ref_reg <= '0'; 324 sel_reg <= '0'; 325 fff_reg <= '0'; 326 out_reg <= '0'; 327 actrows <= (others => '0'); 328 elsif CLK'event and CLK = '1' then 329 chg_reg <= (chg_reg and not cs_cc) or chg; -- Simple charge flag 330 ref_reg <= (ref_reg and not cs_cf) or ref; -- Refresh flag 331 sel_reg <= (sel_reg and not cs_cs) or sel; -- Select flag 332 333 -- cnt_ld must be set only when can't be rar/waw/raw 334 fff_reg <= (fff_reg and (sel_reg or chg_reg or not cnt_mx)) or fff; 335 out_reg <= fff_reg; 336 337 if bnk1 = '1' then 338 actrows(12 downto 0) <= arow; 339 end if; 340 if bnk2 = '1' then 341 actrows(25 downto 13) <= arow; 342 end if; 343 if bnk3 = '1' then 344 actrows(38 downto 26) <= arow; 345 end if; 346 if bnk4 = '1' then 347 actrows(51 downto 39) <= arow; 348 end if; 349 end if; 350 end process; 351 352 ----------------------------------------------------------------------------- 353 -- CMD_loaded control register 354 cmd_ld_reg: process(RST, CLK, cmd_ld_xor1) 355 begin 356 if RST = '1' then 357 cmd_ld_xor2 <= cmd_ld_xor1; 358 elsif (CLK'event and CLK = '0') then 359 cmd_ld_xor2 <= cmd_ld_xor1; 360 end if; 361 end process; 362 363 ----------------------------------------------------------------------------- 364 -- Data from FIFO to SDRAM output 365 data_to_bus: process(RST, CLK) 366 begin 367 if RST = '1' then 368 data_bus_reg <= (others => '0'); 369 column_bus_reg <= (others => '0'); 370 bank_bus_reg <= (others => '0'); 371 row_bus_reg <= (others => '0'); 372 elsif (CLK'event and CLK = '0') then 373 if cmd_loaded = '1' then 374 data_bus_reg <= din_fifo_reg; 375 column_bus_reg <= col_fifo_reg; 376 bank_bus_reg <= bnk_fifo_reg; 377 row_bus_reg <= row_fifo_reg; 378 end if; 379 end if; 380 end process; 381 382 ----------------------------------------------------------------------------- 383 -- Data from input to FIFO, load control flag 384 cmd_ld_work: process(RST, CLK) 385 begin 386 if RST = '1' then 387 cmd_fifo_reg <= fNop; 388 bnk_fifo_reg <= (others => '0'); 389 row_fifo_reg <= (others => '0'); 390 col_fifo_reg <= (others => '0'); 391 din_fifo_reg <= (others => '0'); 392 cmd_ld_xor1 <= '0'; 393 elsif (CLK'event and CLK = '0') then 394 if cmd_ld_en = '1' then 395 cmd_fifo_reg <= CMD; 396 bnk_fifo_reg <= BANK; 397 col_fifo_reg <= ADDR_COLUMN; 398 row_fifo_reg <= ADDR_ROW; 399 din_fifo_reg <= DATA_IN; 400 cmd_ld_xor1 <= not cmd_ld_xor1; 401 end if; 402 end if; 403 end process; 404 405 ----------------------------------------------------------------------------- 406 -- Auto refresh generator 407 ram_refresh_gen: process(RST, CLK) 408 begin 409 if RST = '1' then 410 ref_cnt <= (others => '0'); 411 elsif CLK'event and CLK = '0' then 412 if GEN_AUTO_REFRESH = true then 413 if ref_reg = '1' then -- When ref flag set, reset counter 414 ref_cnt <= (others => '0'); 415 elsif ref_mx = '0' then 416 ref_cnt <= ref_cnt + 1; 417 end if; 418 end if; 419 end if; 420 end process; 421 422 -- Command idle timer 423 ram_cnt: process(RST, CLK) 424 begin 425 if RST = '1' then 426 cnt <= (others => '1'); 427 elsif CLK'event and CLK = '0' then 428 if cnt_load = '1' then 429 cnt <= cnt_set; 430 elsif cnt_mx = '0' then 431 cnt <= cnt + 1; 432 end if; 433 end if; 434 end process; 435 436 -- Data valid shifter (latency), output reg write 437 ram_read_flag: process(RST, CLK) 438 begin 439 if RST = '1' then 440 dout_reg <= (others => '0'); 441 elsif CLK'event and CLK = '1' then 442 -- Output reg set 443 if lat_sh(1) = '1' then 444 dout_reg <= RAM_D; 445 end if; 446 -- Latency shift 447 lat_sh <= lat_sh(1 downto 0) & dout_ready; 448 end if; 449 end process; 450 451 ----------------------------------------------------------------------------- 452 -- Init FSM 453 fsm_init_ctrl: process(RST, CLK) 454 begin 455 if RST = '1' then 456 cstate_init <= csi_Begin; 457 elsif CLK'event and CLK = '0' then 458 cstate_init <= nstate_init; 459 end if; 460 end process; 461 462 fsm_init: process(cstate_init) 463 begin 464 init_p0 <= '0'; 465 init_p1 <= '0'; 466 init_p2 <= '0'; 467 inited <= '0'; 468 469 case cstate_init is 470 when csi_Begin => null; 471 when csi_Idle => init_p0 <= '1'; 472 when csi_Chg => init_p0 <= '1'; 473 when csi_Ref1 => init_p1 <= '1'; 474 when csi_Ref2 => init_p1 <= '1'; 475 when csi_Ref3 => init_p1 <= '1'; 476 when csi_Ref4 => init_p1 <= '1'; 477 when csi_Ref5 => init_p1 <= '1'; 478 when csi_Ref6 => init_p1 <= '1'; 479 when csi_Ref7 => init_p1 <= '1'; 480 when csi_LMR => init_p2 <= '1'; 481 when csi_End => inited <= '1'; 482 end case; 483 end process; 484 485 fsm_init_ns: process(cstate_init, cnt_load) 486 begin 487 nstate_init <= csi_Begin; 488 489 case cstate_init is 490 when csi_Begin => nstate_init <= csi_Idle; 491 when csi_Idle => nstate_init <= csi_Chg; 492 when csi_Chg => 493 if cnt_load = '1' then 494 nstate_init <= csi_Ref1; 495 else 496 nstate_init <= csi_Chg; 497 end if; 498 when csi_Ref1 => 499 if cnt_load = '1' then 500 nstate_init <= csi_Ref2; 501 else 502 nstate_init <= csi_Ref1; 503 end if; 504 when csi_Ref2 => 505 if cnt_load = '1' then 506 nstate_init <= csi_Ref3; 507 else 508 nstate_init <= csi_Ref2; 509 end if; 510 when csi_Ref3 => 511 if cnt_load = '1' then 512 nstate_init <= csi_Ref4; 513 else 514 nstate_init <= csi_Ref3; 515 end if; 516 when csi_Ref4 => 517 if cnt_load = '1' then 518 nstate_init <= csi_Ref5; 519 else 520 nstate_init <= csi_Ref4; 521 end if; 522 when csi_Ref5 => 523 if cnt_load = '1' then 524 nstate_init <= csi_Ref6; 525 else 526 nstate_init <= csi_Ref5; 527 end if; 528 when csi_Ref6 => 529 if cnt_load = '1' then 530 nstate_init <= csi_Ref7; 531 else 532 nstate_init <= csi_Ref6; 533 end if; 534 when csi_Ref7 => 535 if cnt_load = '1' then 536 nstate_init <= csi_LMR; 537 else 538 nstate_init <= csi_Ref7; 539 end if; 540 when csi_LMR => 541 if cnt_load = '1' then 542 nstate_init <= csi_End; 543 else 544 nstate_init <= csi_LMR; 545 end if; 546 when csi_End => nstate_init <= csi_End; 547 end case; 548 end process; 549 550 ----------------------------------------------------------------------------- 551 -- Muxes 552 553 -- Latency 2, Sequential, Burst Len 1B, Single Location Access 554 RAM_A <= (9 => '1', 5 => '1', others => '0') when ram_a_sel = "00" 555 else bank_bus_reg & '0' & (not ref_reg) & "0000000000" when ram_a_sel = "01" 556 else bank_bus_reg & row_bus_reg when ram_a_sel = "10" 557 else bank_bus_reg & "000" & column_bus_reg when ram_a_sel = "11"; 558 559 ----------------------------------------------------------------------------- 560 -- Main FSM control 561 ram_FSM_ctrl: process(RST, CLK) 562 begin 563 if RST = '1' then 564 cstate <= stReset; 565 elsif CLK'event and CLK = '0' then 566 cstate <= nstate; 567 end if; 568 end process; 569 570 -- Main FSM logic 571 ram_FSM: process(cstate, rar, waw, raw) 572 begin 573 -- Default 574 ram_cmd <= "111111"; -- Idle (RCKE RDQM CS RAS CAS WE) 575 cnt_value <= t1clk; -- Counter value 576 cnt_load <= '0'; -- No counter set value 577 dout_ready <= '0'; -- No data reading (from RAM) 578 din_ready <= '0'; -- No data to write (to RAM) 579 ram_a_sel <= (others => '0'); 580 -- CurrentState_Cmd(Charge,reFresh,Select,Idle) 581 cs_cc <= '0'; 582 cs_cf <= '0'; 583 cs_cs <= '0'; 584 cs_cr <= '0'; 585 cs_cw <= '0'; 586 587 case cstate is 588 when stIdle => null; 589 590 when stReset => -- Start 591 ram_cmd <= "011111"; -- RCKE RDQM CS RAS CAS WE 592 593 when stCmdLMR => -- Load mode register (OP-CODE) 594 ram_cmd <= "110000"; 595 ram_a_sel <= "00"; 596 cnt_value <= t1clk; 597 cnt_load <= '1'; 598 599 when stCmdWait => -- External command waiting 600 null; 601 602 when stCmdCharge => -- Precharge 603 cs_cc <= '1'; -- Current state charge identify 604 ram_cmd <= "110010"; 605 ram_a_sel <= "01"; 606 cnt_value <= t2clk; 607 cnt_load <= '1'; 608 609 when stCmdRefresh => -- Refresh 610 cs_cf <= '1'; -- Current state refresh identify 611 ram_cmd <= "110001"; 612 cnt_value <= t7clk; 613 cnt_load <= '1'; 614 615 when stCmdSelect => -- Select bank/row 616 cs_cs <= '1'; -- Current state select identify 617 ram_cmd <= "110011"; 618 ram_a_sel <= "10"; 619 cnt_value <= t3clk; 620 cnt_load <= '1'; 621 622 when stCmdRead => -- Read byte bank/column 623 cs_cr <= '1'; 624 ram_cmd <= "100101"; 625 ram_a_sel <= "11"; 626 dout_ready <= '1'; 627 cnt_value <= t2clk; 628 cnt_load <= not rar; 629 630 when stCmdWrite => -- Write byte bank/column 631 cs_cw <= '1'; 632 ram_cmd <= "100100"; 633 ram_a_sel <= "11"; 634 din_ready <= '1'; 635 cnt_value <= t1clk; 636 cnt_load <= not (waw or raw); 637 638 end case; 639 end process; 640 641 -- Main FSM state control 642 ram_FSM_ns: process(cstate, cnt_mx, rar, waw, raw, init_p0, chg_reg, init_p1, ref_reg, init_p2, sel_reg, out_ld, cmd_as_state) 643 begin 644 -- Default 645 nstate <= stReset; -- Future state, after actual finished 646 647 case cstate is 648 when stIdle => 649 if (not cnt_mx and not (rar or waw or raw)) = '1' then 650 nstate <= stIdle; 651 elsif (init_p0 or chg_reg) = '1' then 652 nstate <= stCmdCharge; 653 elsif (init_p1 or ref_reg) = '1' then 654 nstate <= stCmdRefresh; 655 elsif init_p2 = '1' then 656 nstate <= stCmdLMR; 657 elsif sel_reg = '1' then 658 nstate <= stCmdSelect; 659 elsif out_ld = '1' then 660 nstate <= cmd_as_state; 661 else 662 nstate <= stCmdWait; 663 end if; 664 665 when stReset => nstate <= stIdle; 666 when stCmdLMR => nstate <= stIdle; 667 when stCmdCharge => nstate <= stIdle; 668 when stCmdRefresh => nstate <= stIdle; 669 when stCmdSelect => nstate <= stIdle; 670 671 when stCmdWait => -- External command waiting 672 if chg_reg = '1' then 673 nstate <= stCmdCharge; 674 elsif ref_reg = '1' then 675 nstate <= stCmdRefresh; 676 elsif sel_reg = '1' then 677 nstate <= stCmdSelect; 678 elsif out_ld = '1' then 679 nstate <= cmd_as_state; 680 else 681 nstate <= stCmdWait; 682 end if; 683 684 when stCmdRead => -- Read byte bank/column 685 if rar = '1' then 686 nstate <= stCmdRead; -- Read after read 687 else 688 nstate <= stIdle; 689 end if; 690 691 when stCmdWrite => -- Write byte bank/column 692 if (waw or raw) = '1' then 693 nstate <= cmd_as_state; -- Write/read after write 694 else 695 nstate <= stIdle; 696 end if; 697 698 end case; 699 end process; 700 701 end arch_sdram_raw_controller; 702
Zobrazeno: 793712x Naposledy: 6.6.2023 20:41:40
Dokumenty a zdrojové kódy jsou dostupné pod BSD licencí
© 2006 - 2012 Zdeněk Vašíček, Fakulta informačních technologií VUT Brno