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sdram_ctrl.vhd

   1  -- sdram.vhd: SDRAM second level controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Ladislav Capka <xcapka01 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  use work.sdram_controller_cfg.all;
  49  
  50  -- SYNTH-ISE-9.2: slices=91, slicesFF=107, 4luts=149
  51  entity sdram_controller is
  52     port (
  53        -- Hodiny, reset, ...
  54        CLK     : in std_logic; -- 50 MHz default (for autorefresh)
  55        RST     : in std_logic;
  56        ENABLE  : in std_logic;
  57        BUSY    : out std_logic;
  58  
  59        -- Adresa/data
  60        ADDR        : in std_logic_vector(22 downto 0);
  61  
  62        DATA_OUT    : out std_logic_vector(7 downto 0);
  63        DATA_VLD    : out std_logic; -- DATA_OUT valid
  64        READ_EN     : in std_logic; -- begin read
  65  
  66        DATA_IN     : in std_logic_vector(7 downto 0);
  67        WRITE_EN    : in std_logic; -- begin write
  68  
  69        -- SDRAM
  70        RAM_A      : out std_logic_vector(13 downto 0);
  71        RAM_D      : inout std_logic_vector(7 downto 0);
  72        RAM_DQM    : out std_logic;
  73        RAM_CS     : out std_logic;
  74        RAM_RAS    : out std_logic;
  75        RAM_CAS    : out std_logic;
  76        RAM_WE     : out std_logic;
  77        RAM_CLK    : out std_logic;
  78        RAM_CKE    : out std_logic
  79        );
  80  end sdram_controller;
  81  
  82  architecture arch_sdram_controller of sdram_controller is
  83  
  84     component sdram_raw_controller
  85        generic (
  86           GEN_AUTO_REFRESH : boolean := true;
  87           OPTIMIZE_REFRESH : sdram_optimize := oAlone
  88           );
  89        port (
  90           -- Hodiny, reset, ...
  91           CLK     : in std_logic;
  92           RST     : in std_logic;
  93           ENABLE  : in std_logic;
  94           BUSY    : out std_logic;
  95  
  96           -- Adresa/data
  97           ADDR_ROW    : in std_logic_vector(11 downto 0);
  98           ADDR_COLUMN : in std_logic_vector(8 downto 0);
  99           BANK        : in std_logic_vector(1 downto 0);
 100           DATA_IN     : in std_logic_vector(7 downto 0);
 101           DATA_OUT    : out std_logic_vector(7 downto 0);
 102           DATA_VLD    : out std_logic; -- Output data valid
 103  
 104           -- Pozadavek + jeho potvrzeni
 105           CMD     : in sdram_func;
 106           CMD_WE  : in std_logic;
 107  
 108           -- SDRAM
 109           RAM_A      : out std_logic_vector(13 downto 0);
 110           RAM_D      : inout std_logic_vector(7 downto 0);
 111           RAM_DQM    : out std_logic;
 112           RAM_CS     : out std_logic;
 113           RAM_RAS    : out std_logic;
 114           RAM_CAS    : out std_logic;
 115           RAM_WE     : out std_logic;
 116           RAM_CLK    : out std_logic;
 117           RAM_CKE    : out std_logic
 118        );
 119     end component;
 120  
 121     signal cmd            : sdram_func;
 122     signal cmd_set        : std_logic;
 123     signal we_x           : std_logic;
 124     signal re_x           : std_logic;
 125     signal we_x2          : std_logic;
 126     signal re_x2          : std_logic;
 127     signal we_mx          : std_logic;
 128     signal re_mx          : std_logic;
 129     signal aCol           : std_logic_vector(8 downto 0);
 130     signal aRow           : std_logic_vector(11 downto 0);
 131     signal aBank          : std_logic_vector(1 downto 0);
 132  
 133  begin
 134  
 135     aCol <= ADDR(8 downto 0);
 136     aRow <= ADDR(20 downto 9);
 137     aBank <= ADDR(22 downto 21);
 138  
 139     -- SDRAM
 140     raw_sdram: sdram_raw_controller
 141        generic map (
 142           GEN_AUTO_REFRESH => true,
 143           OPTIMIZE_REFRESH => oAlone
 144           )
 145        port map (
 146           -- Hodiny, reset, ...
 147           CLK         => CLK,
 148           RST         => RST,
 149           ENABLE      => ENABLE,
 150           BUSY        => BUSY,
 151  
 152           -- Adresa/data
 153           ADDR_COLUMN => aCol,
 154           ADDR_ROW    => aRow,
 155           BANK        => aBank,
 156           DATA_IN     => DATA_IN,
 157           DATA_OUT    => DATA_OUT,
 158           DATA_VLD    => DATA_VLD,
 159  
 160           -- Pozadavek + jeho potvrzeni
 161           CMD      => cmd,
 162           CMD_WE   => cmd_set,
 163  
 164           -- SDRAM
 165           RAM_A       => RAM_A,
 166           RAM_D       => RAM_D,
 167           RAM_DQM     => RAM_DQM,
 168           RAM_CS      => RAM_CS,
 169           RAM_RAS     => RAM_RAS,
 170           RAM_CAS     => RAM_CAS,
 171           RAM_WE      => RAM_WE,
 172           RAM_CLK     => RAM_CLK,
 173           RAM_CKE     => RAM_CKE
 174        );
 175  
 176     -- SPI_WE/RE
 177     detect: process(CLK, RST)
 178     begin
 179       if RST = '1' then
 180           we_x <= '0';
 181           re_x <= '0';
 182           we_x2 <= '0';
 183           re_x2 <= '0';
 184       elsif CLK'event and CLK = '1' then
 185           we_x2 <= we_x;
 186           re_x2 <= re_x;
 187           we_x <= WRITE_EN;
 188           re_x <= READ_EN;
 189       end if;
 190     end process;
 191  
 192     -- Detekce R/W
 193     we_mx <= (not we_x2 and we_x);
 194     re_mx <= (not re_x2 and re_x);
 195  
 196     -- Odesilani prikazu R/W do radice RAM
 197     ram_send_cmd: process(CLK, RST)
 198     begin
 199       if RST = '1' then
 200          cmd <= fNop;
 201          cmd_set <= '0';
 202       elsif CLK'event and CLK = '1' then
 203           cmd_set <= '0';
 204           if re_mx = '1' then
 205              -- Read
 206              cmd <= fRead;
 207              cmd_set <= '1';
 208           elsif we_mx = '1' then
 209              -- Write
 210              cmd <= fWrite;
 211              cmd_set <= '1';
 212           end if;
 213       end if;
 214     end process;
 215  
 216  end arch_sdram_controller;
 217  
Zobrazeno: 679765x Naposledy: 28.6.2022 20:21:32