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ps2half_ctrl.vhd

   1  -- ps2half_ctrl.vhd: Simple PS/2 Controller (readonly version)
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  library IEEE;
  44  use IEEE.STD_LOGIC_1164.ALL;
  45  use IEEE.STD_LOGIC_ARITH.ALL;
  46  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  47  
  48  architecture half of PS2_controller is
  49  
  50     type    FSMstate is (SInit, SRcvData, SRcvParity, SRcvStop);
  51     signal  pstate    : FSMstate; -- actual state
  52     signal  nstate    : FSMstate; -- next state
  53  
  54     signal  ps2clk_reg  : std_logic;
  55     signal  ps2clk_dreg : std_logic;
  56     signal  ps2data_reg : std_logic;
  57     signal  di_en       : std_logic; --read from PS/2 data
  58  
  59     signal bitcntr     : std_logic_vector(7 downto 0);
  60     signal bitcntr_en  : std_logic;
  61     signal bitcntr_rst : std_logic;
  62     signal bits_cmp8   : std_logic;
  63  
  64     signal datain_reg  : std_logic_vector(7 downto 0);
  65     signal datain_en   : std_logic;
  66     signal datain_rst  : std_logic;
  67     signal datain_parity : std_logic;
  68  
  69  begin
  70     PS2_CLK   <= 'Z';
  71     PS2_DATA  <= 'Z';
  72  
  73     DATA_OUT  <= datain_reg;
  74  
  75     -- PS/2 CLK edge detector
  76     process (RST, CLK)
  77     begin
  78        if (RST = '1') then
  79           ps2clk_reg  <= '1';
  80           ps2clk_dreg <= '1';
  81           ps2data_reg <= '1';
  82        elsif (CLK'event) and (CLK = '1') then
  83           ps2clk_reg  <= PS2_CLK;
  84           ps2clk_dreg <= ps2clk_reg;
  85           ps2data_reg <= PS2_DATA;
  86        end if;
  87     end process;
  88  
  89     di_en <= ps2clk_dreg and (not ps2clk_reg);
  90  
  91     -- Bits counter
  92     bitscntr: process(RST, CLK)
  93     begin
  94        if (RST = '1') then
  95           bitcntr <= (others => '0');
  96        elsif (CLK'event) and (CLK='1') then
  97           if (bitcntr_rst = '1') then
  98              bitcntr <= (others => '0');
  99           elsif (bitcntr_en='1') then
 100              bitcntr <= bitcntr + 1;
 101           end if;
 102        end if;
 103     end process;
 104  
 105     -- Comparators
 106     bits_cmp8   <= '1' when (bitcntr = 16#08#) else '0';
 107  
 108     --DataIN shift register
 109     process (RST, CLK)
 110     begin
 111        if (RST = '1') then
 112           --datain_reg <= (others=>'0');
 113        elsif (CLK'event) and (CLK = '1') then
 114           if (datain_en='1') then
 115              datain_reg <= ps2data_reg & datain_reg(7 downto 1);
 116           end if;
 117        end if;
 118     end process;
 119  
 120     --DataIN odd parity
 121     process (RST, CLK)
 122     begin
 123        if (RST = '1') then
 124           datain_parity <= '1';
 125        elsif (CLK'event) and (CLK = '1') then
 126           if (datain_rst = '1') then
 127              datain_parity <= '1';
 128           elsif (datain_en='1') then
 129              datain_parity <= datain_parity xor ps2data_reg;
 130           end if;
 131        end if;
 132     end process;
 133  
 134     --FSM present state
 135     process (RST, CLK)
 136     begin
 137        if (RST = '1') then
 138           pstate <= sinit;
 139        elsif (CLK'event) and (CLK = '1') then
 140           pstate <= nstate;
 141        end if;
 142     end process;
 143  
 144     --FSM next state logic
 145     process (pstate, di_en, ps2data_reg, datain_parity, bits_cmp8)
 146     begin
 147        nstate <= SInit;
 148        bitcntr_rst <= '0';
 149        bitcntr_en <= '0';
 150        datain_en <= '0';
 151        datain_rst <= '0';
 152        DATA_ERR <= '0';
 153        DATA_VLD <= '0';
 154  
 155        case pstate is
 156           when SInit =>
 157              if (di_en='1') and (ps2data_reg='0') then
 158                 nstate <= SRcvData;
 159                 bitcntr_rst <= '1';
 160                 datain_rst <= '1';
 161              end if;
 162  
 163           --Receive data bits
 164           when SRcvData =>
 165              if (bits_cmp8='0') then
 166                 nstate <= SRcvData;
 167                 bitcntr_en <= di_en;
 168                 datain_en <= di_en;
 169              else
 170                 nstate <= SRcvParity;
 171              end if;
 172  
 173           -- Receive parity
 174           when SRcvParity =>
 175              if (di_en='1') then
 176                 nstate <= SRcvStop;
 177                 assert (ps2data_reg=datain_parity) report "PS/2 Data Parity Error" severity note;
 178                 if (ps2data_reg=datain_parity) then
 179                    DATA_VLD <= '1';
 180                 else
 181                    DATA_ERR <= '1';
 182                 end if;
 183              else
 184                 nstate <= SRcvParity;
 185              end if;
 186  
 187           -- Receive stop bit
 188           when SRcvStop =>
 189              if (di_en='0') then
 190                 nstate <= SRcvStop;
 191              end if;
 192  
 193           when others =>
 194              null;
 195        end case;
 196     end process;
 197  end half;
 198  
 199  
Zobrazeno: 679740x Naposledy: 28.6.2022 19:52:25