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Aktuální adresář: FITkit / trunk / fpga / ctrls / lcd /

lcd_fsm_main.vhd

   1  -- lcd_fsm_main.vhd : LCD controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Tomas Martinek <martinto AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  -- Functional description:
  43  -- =======================
  44  -- * when READ operation is required, the FSM waits until read cycle finish
  45  --   and then goes to the IDLE state
  46  -- * when WRITE operation is required then:
  47  --       * FSM waits until write cycle finish
  48  --       * FSM reads LCD Busy flag repeatly until flag goes low
  49  --       * FSM waits several clock cycles before next read of write operation
  50  --
  51  library IEEE;
  52  use IEEE.STD_LOGIC_1164.all;
  53  use IEEE.STD_LOGIC_ARITH.all;
  54  use IEEE.STD_LOGIC_UNSIGNED.all;
  55  -- ------------------------------------------------------------------
  56  --                      Entity Declaration
  57  -- ------------------------------------------------------------------
  58  entity lcd_fsm_main is
  59     port (
  60        RESET       : in  std_logic;
  61        CLK         : in  std_logic;
  62  
  63        -- input signals
  64        READ        : in  std_logic;
  65        WRITE       : in  std_logic;
  66        LCD_BUSY    : in  std_logic;
  67        FSMC_BUSY   : in  std_logic;
  68  
  69        -- output signals
  70        FSM_REQ     : out std_logic;
  71        FSM_DV      : out std_logic;
  72        FSM_RDBF    : out std_logic;
  73        FSM_BUSY    : out std_logic
  74  );
  75  end lcd_fsm_main;
  76  -- ------------------------------------------------------------------
  77  --                    Architecture Declaration
  78  -- ------------------------------------------------------------------
  79  architecture behavioral of lcd_fsm_main is
  80     type t_state is (IDLE, READ_OP, WRITE_OP, READ_BUSY, READ_WAIT);
  81     signal present_state, next_state : t_state;
  82     signal cnt_rdwait    : std_logic_vector(3 downto 0);
  83     signal cnt_rdwait_ce : std_logic;
  84     signal cnt_rdwait_of : std_logic;
  85  
  86  begin
  87  
  88  -- cnt_rdwait counter
  89  process(RESET, CLK)
  90  begin
  91     if (RESET = '1') then
  92        cnt_rdwait <= (others => '0');
  93     elsif (CLK'event AND CLK = '1') then
  94        if (cnt_rdwait_ce = '1') then
  95           cnt_rdwait <= cnt_rdwait + 1;
  96        end if;
  97     end if;
  98  end process;
  99  
 100  cnt_rdwait_of <= '1' when (cnt_rdwait = "1111") else '0';
 101  
 102  -- -------------------------------------------------------
 103  sync_logic : process(RESET, CLK)
 104  begin
 105     if (RESET = '1') then
 106        present_state <= IDLE;
 107     elsif (CLK'event AND CLK = '1') then
 108        present_state <= next_state;
 109     end if;
 110  end process sync_logic;
 111  
 112  -- -------------------------------------------------------
 113  next_state_logic : process(present_state, READ, WRITE, FSMC_BUSY, LCD_BUSY,
 114                             cnt_rdwait_of)
 115  begin
 116     case (present_state) is
 117     -- - - - - - - - - - - - - - - - - - - - - - -
 118     when IDLE =>
 119        next_state <= IDLE;
 120        if (READ='1') then
 121           next_state <= READ_OP;
 122        elsif (WRITE='1') then
 123           next_state <= WRITE_OP;
 124        end if;
 125     -- - - - - - - - - - - - - - - - - - - - - - -
 126     when READ_OP =>
 127        next_state <= READ_OP;
 128        if (FSMC_BUSY='0') then
 129           next_state <= IDLE;
 130        end if;
 131     -- - - - - - - - - - - - - - - - - - - - - - -
 132     when WRITE_OP =>
 133        next_state <= WRITE_OP;
 134        if (FSMC_BUSY='0') then
 135           next_state <= READ_BUSY;
 136        end if;
 137     -- - - - - - - - - - - - - - - - - - - - - - -
 138     when READ_BUSY =>
 139        next_state <= READ_BUSY;
 140        if (FSMC_BUSY='0' and LCD_BUSY='0') then
 141           next_state <= READ_WAIT;
 142        end if;
 143     -- - - - - - - - - - - - - - - - - - - - - - -
 144     when READ_WAIT =>
 145        next_state <= READ_WAIT;
 146        if (cnt_rdwait_of='1') then
 147           next_state <= IDLE;
 148        end if;
 149     -- - - - - - - - - - - - - - - - - - - - - - -
 150     when others =>
 151        next_state <= IDLE;
 152     end case;
 153  end process next_state_logic;
 154  
 155  -- -------------------------------------------------------
 156  output_logic : process(present_state, READ, WRITE, FSMC_BUSY, LCD_BUSY)
 157  begin
 158     FSM_REQ  <= '0';
 159     FSM_DV   <= '0';
 160     FSM_RDBF <= '0';
 161     FSM_BUSY <= '1';
 162     cnt_rdwait_ce <= '0';
 163  
 164     case (present_state) is
 165     -- - - - - - - - - - - - - - - - - - - - - - -
 166     when IDLE =>
 167        FSM_BUSY <= '0';
 168        if (READ='1' or WRITE='1') then
 169           FSM_REQ <= '1';
 170        end if;
 171     -- - - - - - - - - - - - - - - - - - - - - - -
 172     when READ_OP =>
 173        if (FSMC_BUSY='0') then
 174           FSM_DV <= '1';
 175        end if;
 176     -- - - - - - - - - - - - - - - - - - - - - - -
 177     when WRITE_OP =>
 178        if (FSMC_BUSY='0') then
 179           FSM_RDBF <= '1';
 180           FSM_REQ  <= '1';
 181        end if;
 182     -- - - - - - - - - - - - - - - - - - - - - - -
 183     when READ_BUSY =>
 184        if (FSMC_BUSY='0' and LCD_BUSY='1') then
 185           FSM_RDBF <= '1';
 186           FSM_REQ  <= '1';
 187        end if;
 188     -- - - - - - - - - - - - - - - - - - - - - - -
 189     when READ_WAIT=>
 190        cnt_rdwait_ce <= '1';
 191     -- - - - - - - - - - - - - - - - - - - - - - -
 192     when others =>
 193     end case;
 194  end process output_logic;
 195  
 196  end behavioral;
 197  
 198  
Zobrazeno: 679481x Naposledy: 25.6.2022 22:19:56