Čeština / English
Login

SVN Repository / Prohlížení

Aktuální adresář: FITkit / trunk / fpga / ctrls / lcd /

lcd_fsm_cycle.vhd

   1  -- lcd_fsm_cycle.vhd : LCD controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --            Tomas Martinek <martinto AT fit.vutbr.cz>
   6  --
   7  -- LICENSE TERMS
   8  --
   9  -- Redistribution and use in source and binary forms, with or without
  10  -- modification, are permitted provided that the following conditions
  11  -- are met:
  12  -- 1. Redistributions of source code must retain the above copyright
  13  --    notice, this list of conditions and the following disclaimer.
  14  -- 2. Redistributions in binary form must reproduce the above copyright
  15  --    notice, this list of conditions and the following disclaimer in
  16  --    the documentation and/or other materials provided with the
  17  --    distribution.
  18  -- 3. All advertising materials mentioning features or use of this software
  19  --    or firmware must display the following acknowledgement:
  20  --
  21  --      This product includes software developed by the University of
  22  --      Technology, Faculty of Information Technology, Brno and its
  23  --      contributors.
  24  --
  25  -- 4. Neither the name of the Company nor the names of its contributors
  26  --    may be used to endorse or promote products derived from this
  27  --    software without specific prior written permission.
  28  --
  29  -- This software or firmware is provided ``as is'', and any express or implied
  30  -- warranties, including, but not limited to, the implied warranties of
  31  -- merchantability and fitness for a particular purpose are disclaimed.
  32  -- In no event shall the company or contributors be liable for any
  33  -- direct, indirect, incidental, special, exemplary, or consequential
  34  -- damages (including, but not limited to, procurement of substitute
  35  -- goods or services; loss of use, data, or profits; or business
  36  -- interruption) however caused and on any theory of liability, whether
  37  -- in contract, strict liability, or tort (including negligence or
  38  -- otherwise) arising in any way out of the use of this software, even
  39  -- if advised of the possibility of such damage.
  40  --
  41  -- $Id$
  42  --
  43  --
  44  
  45  library IEEE;
  46  use IEEE.STD_LOGIC_1164.all;
  47  use IEEE.STD_LOGIC_ARITH.all;
  48  use IEEE.STD_LOGIC_UNSIGNED.all;
  49  
  50  -- ------------------------------------------------------------------
  51  --                      Entity Declaration
  52  -- ------------------------------------------------------------------
  53  entity lcd_fsm_cycle is
  54     port (
  55        RESET    : in std_logic;
  56        CLK      : in std_logic;
  57  
  58        -- input signals
  59        REQ      : in std_logic;
  60        REG_RW   : in std_logic;
  61  
  62        -- output signals
  63        FSM_LE   : out   std_logic;
  64        FSM_RW   : out   std_logic;
  65        FSM_DV   : out   std_logic;
  66        FSM_TS   : out   std_logic;
  67        FSM_BUSY : out   std_logic
  68  );
  69  end lcd_fsm_cycle;
  70  
  71  -- ------------------------------------------------------------------
  72  --                    Architecture Declaration
  73  -- ------------------------------------------------------------------
  74  architecture behavioral of lcd_fsm_cycle is
  75     type t_state is (IDLE,  T0, T1, T2, T3, T4, T5, T6, T7, T8, T9);
  76     signal present_state, next_state : t_state;
  77  
  78  begin
  79  
  80  -- -------------------------------------------------------
  81  sync_logic : process(RESET, CLK)
  82  begin
  83     if (RESET = '1') then
  84        present_state <= IDLE;
  85     elsif (CLK'event AND CLK = '1') then
  86        present_state <= next_state;
  87     end if;
  88  end process sync_logic;
  89  
  90  -- -------------------------------------------------------
  91  next_state_logic : process(present_state, REQ)
  92  begin
  93     case (present_state) is
  94     when IDLE =>
  95        next_state <= IDLE;
  96        if (REQ='1') then
  97           next_state <= T0;
  98        end if;
  99     when T0 => next_state <= T1;
 100     when T1 => next_state <= T2;
 101     when T2 => next_state <= T3;
 102     when T3 => next_state <= T4;
 103     when T4 => next_state <= T5;
 104     when T5 => next_state <= T6;
 105     when T6 => next_state <= T7;
 106     when T7 => next_state <= T8;
 107     when T8 => next_state <= T9;
 108     when T9 => next_state <= IDLE;
 109     when others =>
 110        next_state <= IDLE;
 111     end case;
 112  end process next_state_logic;
 113  
 114  -- -------------------------------------------------------
 115  output_logic : process(present_state, REG_RW)
 116  begin
 117     FSM_RW   <= '1';
 118     FSM_LE   <= '0';
 119     FSM_DV   <= '0';
 120     FSM_BUSY <= '1';
 121     FSM_TS   <= '1';
 122  
 123     case (present_state) is
 124     when IDLE =>
 125        FSM_BUSY <= '0';
 126     when T0 =>
 127        FSM_RW   <= REG_RW;
 128     when T1 =>
 129        FSM_RW   <= REG_RW;
 130     when T2 =>
 131        FSM_LE   <= '1';
 132        FSM_RW   <= REG_RW;
 133     when T3 =>
 134        FSM_LE   <= '1';
 135        FSM_TS   <= REG_RW;
 136        FSM_RW   <= REG_RW;
 137     when T4 =>
 138        FSM_LE   <= '1';
 139        FSM_TS   <= REG_RW;
 140        FSM_RW   <= REG_RW;
 141     when T5 =>
 142        FSM_LE   <= '1';
 143        FSM_TS   <= REG_RW;
 144        FSM_DV   <= REG_RW;
 145        FSM_RW   <= REG_RW;
 146     when T6 =>
 147        FSM_TS   <= REG_RW;
 148        FSM_RW   <= REG_RW;
 149     when T7 =>
 150        FSM_TS   <= REG_RW;
 151        FSM_RW   <= REG_RW;
 152     when T8 =>
 153     when T9 =>
 154     when others =>
 155     end case;
 156  end process output_logic;
 157  
 158  end behavioral;
 159  
 160  
Zobrazeno: 679458x Naposledy: 25.6.2022 21:22:35