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lcd_ctrl_rw.vhd

   1  -- lcd_ctrl_rw.vhd : LCD base controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Tomas Martinek <martinto AT fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.STD_LOGIC_1164.all;
  46  use IEEE.STD_LOGIC_ARITH.all;
  47  use IEEE.STD_LOGIC_UNSIGNED.all;
  48  
  49  -- ------------------------------------------------------------------
  50  --                      Entity Declaration
  51  -- ------------------------------------------------------------------
  52  entity lcd_ctrl_rw is
  53     port (
  54        RESET    : in std_logic;
  55        CLK      : in std_logic;
  56  
  57        -- interni rozhrani
  58        READ     : in std_logic;
  59        WRITE    : in std_logic;
  60        RS       : in std_logic;
  61        DIN      : in  std_logic_vector(7 downto 0);
  62        DOUT     : out std_logic_vector(7 downto 0);
  63        DV       : out std_logic;
  64        BUSY     : out std_logic;
  65  
  66        --- rozhrani LCD displeje
  67        LRS      : out   std_logic;
  68        LRW      : out   std_logic;
  69        LE       : out   std_logic;
  70        LD       : inout std_logic_vector(7 downto 0)
  71  );
  72  
  73  end lcd_ctrl_rw;
  74  
  75  -- ------------------------------------------------------------------
  76  --                    Architecture Declaration
  77  -- ------------------------------------------------------------------
  78  architecture behavioral of lcd_ctrl_rw is
  79  
  80     signal reg_data_in      : std_logic_vector(7 downto 0);
  81     signal reg_data_in_we   : std_logic;
  82     signal reg_data_out     : std_logic_vector(7 downto 0);
  83     signal reg_data_out_we  : std_logic;
  84     signal reg_rs           : std_logic;
  85     signal reg_rs_we        : std_logic;
  86     signal reg_rw           : std_logic;
  87     signal reg_rw_we        : std_logic;
  88  
  89     signal fsm_cycle_dv     : std_logic;
  90     signal fsm_cycle_rw     : std_logic;
  91     signal fsm_cycle_ts     : std_logic;
  92     signal fsm_cycle_busy   : std_logic;
  93  
  94     signal fsm_main_rdbf    : std_logic;
  95     signal fsm_main_req     : std_logic;
  96     signal fsm_main_dv      : std_logic;
  97     signal fsm_main_busy    : std_logic;
  98     signal fsm_main_read    : std_logic;
  99     signal fsm_main_write   : std_logic;
 100  
 101  begin
 102  -- ------------------------------------------------------------------
 103  --                           Registers
 104  -- ------------------------------------------------------------------
 105  
 106  -- reg_data_in register
 107  reg_data_in_we <= WRITE and (not fsm_cycle_busy);
 108  process(RESET, CLK)
 109  begin
 110     if (RESET = '1') then
 111        reg_data_in <= (others => '0');
 112     elsif (CLK'event AND CLK = '1') then
 113        if (reg_data_in_we = '1') then
 114           reg_data_in <= DIN;
 115        end if;
 116     end if;
 117  end process;
 118  
 119  -- reg_data_out register
 120  reg_data_out_we <= fsm_cycle_dv;
 121  process(RESET, CLK)
 122  begin
 123     if (RESET = '1') then
 124        reg_data_out <= (others => '0');
 125     elsif (CLK'event AND CLK = '1') then
 126        if (reg_data_out_we = '1') then
 127           reg_data_out <= LD;
 128        end if;
 129     end if;
 130  end process;
 131  
 132  -- reg_rs register
 133  reg_rs_we <= (READ or WRITE or fsm_main_rdbf) and (not fsm_cycle_busy);
 134  process(RESET, CLK)
 135  begin
 136     if (RESET = '1') then
 137        reg_rs <= '0';
 138     elsif (CLK'event AND CLK = '1') then
 139        if (reg_rs_we = '1') then
 140           reg_rs <= RS and (not fsm_main_rdbf);
 141        end if;
 142     end if;
 143  end process;
 144  
 145  -- reg_rw register
 146  reg_rw_we <= (READ or WRITE or fsm_main_rdbf) and (not fsm_cycle_busy);
 147  process(RESET, CLK)
 148  begin
 149     if (RESET = '1') then
 150        reg_rw <= '0';
 151     elsif (CLK'event AND CLK = '1') then
 152        if (reg_rw_we = '1') then
 153           reg_rw <= (READ and (not WRITE)) or fsm_main_rdbf;
 154        end if;
 155     end if;
 156  end process;
 157  
 158  -- Output mapping
 159  LRS   <= reg_rs;
 160  LRW   <= fsm_cycle_rw;
 161  LD    <= (others => 'Z') when (fsm_cycle_ts = '1') else reg_data_in;
 162  
 163  DOUT  <= reg_data_out;
 164  BUSY  <= fsm_main_busy;
 165  DV    <= fsm_main_dv;
 166  
 167  -- ------------------------------------------------------------------
 168  --            Finite State Machine - Read/Write Cycle
 169  -- ------------------------------------------------------------------
 170  fsm_main_read  <= READ  and (not fsm_main_busy);
 171  fsm_main_write <= WRITE and (not fsm_main_busy);
 172  
 173  FSM_MAIN : entity work.lcd_fsm_main
 174  port map(
 175     RESET       => RESET,
 176     CLK         => CLK,
 177  
 178     -- input signals
 179     READ        => fsm_main_read,
 180     WRITE       => fsm_main_write,
 181     LCD_BUSY    => reg_data_out(7),
 182     FSMC_BUSY   => fsm_cycle_busy,
 183  
 184     -- output signals
 185     FSM_REQ     => fsm_main_req,
 186     FSM_DV      => fsm_main_dv,
 187     FSM_RDBF    => fsm_main_rdbf,
 188     FSM_BUSY    => fsm_main_busy
 189  );
 190  
 191  -- ------------------------------------------------------------------
 192  --              Finite State Machine - Protocol Cycle
 193  -- ------------------------------------------------------------------
 194  FSM_CYCLE : entity work.lcd_fsm_cycle
 195  port map(
 196     RESET    => RESET,
 197     CLK      => CLK,
 198  
 199     -- interni rozhrani
 200     REQ      => fsm_main_req,
 201     REG_RW   => reg_rw,
 202  
 203     --- rozhrani LCD displeje
 204     FSM_LE   => LE,
 205     FSM_DV   => fsm_cycle_dv,
 206     FSM_TS   => fsm_cycle_ts,
 207     FSM_RW   => fsm_cycle_rw,
 208     FSM_BUSY => fsm_cycle_busy
 209  );
 210  
 211  end behavioral;
 212  
 213