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lcd_ctrl.vhd

   1  -- lcd_ctrl.vhd : LCD base controller
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  -- SYNTH-ISE: slices=7, slicesFF=13, 4luts=6
  45  library IEEE;
  46  use IEEE.STD_LOGIC_1164.all;
  47  use IEEE.STD_LOGIC_ARITH.all;
  48  use IEEE.STD_LOGIC_UNSIGNED.all;
  49  
  50  entity lcd_controller is
  51     port (
  52        RST      : in std_logic;
  53        CLK      : in std_logic;
  54  
  55        -- interni rozhrani
  56        RS       : in std_logic;
  57        DATA_IN  : in std_logic_vector (7 downto 0);
  58        WRITE_EN : in std_logic; -- zapis, okamzik planosti RS, DATA_IN (pokud radic prave zpracovava, je zapis zahozen)
  59        --DATA_OUT  : in std_logic_vector (7 downto 0);
  60        --READ_EN  : in std_logic;
  61  
  62        --- rozhrani LCD displeje
  63        DISPLAY_RS   : out   std_logic;
  64        DISPLAY_DATA : inout std_logic_vector(7 downto 0);
  65        DISPLAY_RW   : out   std_logic;
  66        DISPLAY_EN   : out   std_logic
  67  );
  68  
  69  end lcd_controller;
  70  
  71  architecture base of lcd_controller is
  72  
  73     type FSMState is (idle,  w0, w1, w2, w3, w4, w5, w6, w7);
  74  
  75     signal pstate : FSMState; -- FSM present state
  76     signal nstate : FSMState; -- FSM next state
  77     signal data_reg : std_logic_vector(7 downto 0);
  78     signal datareg_en : std_logic;
  79     signal rs_reg   : std_logic;
  80     signal data_sel : std_logic;
  81  
  82  begin
  83     DISPLAY_RS <= rs_reg;
  84     DISPLAY_DATA <= data_reg when (data_sel='1') else (others => 'Z');
  85  
  86     -- data register
  87     process(CLK, RST)
  88     begin
  89        if (RST = '1') then
  90           data_reg <= (others => '0');
  91           rs_reg <= '0';
  92        elsif (CLK='1') and (CLK'event) then
  93           if (WRITE_EN='1') and (datareg_en='1') then
  94              data_reg <= DATA_IN;
  95              rs_reg <= RS;
  96           end if;
  97        end if;
  98     end process;
  99  
 100     -- FSM present state
 101     process(CLK, RST)
 102     begin
 103        if (RST = '1') then
 104           pstate <= idle;
 105        elsif (CLK='1') and (CLK'event) then
 106           pstate <= nstate;
 107        end if;
 108     end process;
 109  
 110     -- FSM next state logic, output logic
 111     process(pstate, WRITE_EN)
 112     begin
 113        nstate <= idle;
 114        DISPLAY_RW <= '1';
 115        DISPLAY_EN <= '0';
 116        data_sel <= '0';
 117        datareg_en <= '0';
 118  
 119        case pstate is
 120           when idle =>
 121              datareg_en <= '1';
 122              if (WRITE_EN = '1') then
 123                 nstate <= w0;
 124              end if;
 125  
 126           when w0 =>
 127              nstate <= w1;
 128              DISPLAY_RW <= '0';
 129  
 130           when w1 =>
 131              nstate <= w2;
 132              DISPLAY_RW <= '0';
 133  
 134           when w2 =>
 135              nstate <= w3;
 136              DISPLAY_RW <= '0';
 137              DISPLAY_EN <= '1';
 138  
 139           when w3 =>
 140              nstate <= w4;
 141              DISPLAY_RW <= '0';
 142              DISPLAY_EN <= '1';
 143              data_sel <= '1';
 144  
 145           when w4 =>
 146              nstate <= w5;
 147              DISPLAY_RW <= '0';
 148              DISPLAY_EN <= '1';
 149              data_sel <= '1';
 150  
 151           when w5 =>
 152              nstate <= w6;
 153              DISPLAY_RW <= '0';
 154              DISPLAY_EN <= '1';
 155              data_sel <= '1';
 156  
 157           when w6 =>
 158              nstate <= w7;
 159              DISPLAY_RW <= '0';
 160              data_sel <= '1';
 161  
 162           when w7 =>
 163              data_sel <= '1';
 164              DISPLAY_RW <= '0';
 165  
 166        end case;
 167     end process;
 168  
 169  end base;
 170  
 171