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display_base.vhd

   1  -- Display_base.vhd : <short description>
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Jan Markovic   xmarko04@stud.fit.vutbr.cz
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.STD_LOGIC_1164.ALL;
  46  use IEEE.STD_LOGIC_ARITH.ALL;
  47  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  48  
  49  ---- Uncomment the following library declaration if instantiating
  50  ---- any Xilinx primitives in this code.
  51  --library UNISIM;
  52  --use UNISIM.VComponents.all;
  53  
  54  entity Display_base is
  55     generic (
  56        INT_EN : std_logic := '0'
  57     );
  58     Port(
  59        reset     : in std_logic;
  60        clk       : in std_logic;
  61  
  62        --addr      : out  STD_LOGIC_VECTOR (N-1 downto 0);
  63        --data_out  : out  STD_LOGIC_VECTOR (7 downto 0);
  64        RS        : in  STD_LOGIC;
  65        data_in   : in  STD_LOGIC_VECTOR (7 downto 0);
  66        WRITE_EN  : in  STD_LOGIC;
  67        --READ_EN   : in  STD_LOGIC;
  68  
  69        -- ouuput intrrupt
  70        INTERRUPT : out STD_LOGIC;
  71  
  72        -- DISPLAY
  73        RS_dis    : out   std_logic;
  74        data_dis  : inout std_logic_vector (7 downto 0) ;
  75        RW_dis    : out   std_logic;
  76        E_dis     : out   std_logic
  77     );
  78  end Display_base;
  79  
  80  architecture Arch_Display_base of Display_base is
  81  
  82  --TYPI
  83  type State_display_type is (
  84     idle,
  85     w0, w1, w2, w3, w4, w5, w6, w7, r1, r2, r3, r4, r5, r6, r7
  86  );
  87  
  88  -- SIGMALY
  89  signal d_state : State_display_type;
  90  signal data    : std_logic_vector(7 downto 0);
  91  signal dis_busy: std_logic;
  92  signal interrupt_out : std_logic;
  93  
  94  begin
  95  
  96     INTERRUPT  <= INT_EN and interrupt_out;
  97  
  98  state_machyne_display:process(clk,reset)
  99  begin
 100     if reset = '1' then
 101       data  <= "00000000";
 102       RS_dis  <= '0';
 103       data_dis <= "ZZZZZZZZ";
 104       RW_dis  <= '1';
 105       E_dis  <= '0';
 106       dis_busy <= '0';
 107       d_state <= idle;
 108       interrupt_out <= '0';
 109    else
 110       if clk'event and clk = '1' then
 111          interrupt_out <= '0';
 112          case d_state is
 113             when idle =>
 114                if WRITE_EN = '1' then
 115                   d_state <= w0;
 116  --                 busy    <= '0';
 117                   RS_dis  <= RS;
 118                   data    <= data_in;
 119                end if;
 120             when w0 =>
 121                d_state <= w1;
 122                RW_dis  <= '0';
 123             when w1 =>
 124                d_state <= w2;
 125  --              RW_dis <= '0';
 126             when w2 =>
 127                d_state <= w3;
 128                E_dis <= '1';
 129             when w3 =>
 130                d_state <= w4;
 131                data_dis <= data;
 132             when w4 =>
 133                d_state <= w5;
 134             when w5 =>
 135                d_state <= w6;
 136             when w6 =>
 137                E_dis <= '0';
 138                d_state <= w7;
 139             when w7 =>
 140                data_dis <= "ZZZZZZZZ";
 141                RW_dis <= '1';
 142                if INT_EN = '0' then
 143                   d_state <= idle;
 144                else
 145                   d_state <= r1;
 146                end if;
 147  --            -- busy <= '1';
 148  
 149                 -- wiat for busy
 150             when r1 =>
 151                d_state <= r2;
 152                RS_dis  <= '0'; -- read busy flag & addr
 153                RW_dis  <= '1';
 154             when r2 =>
 155                d_state <= r3;
 156                E_dis  <= '1';
 157             when r3 =>
 158                d_state <= r4;
 159             when r4 =>
 160                d_state <= r5;
 161             when r5 =>
 162                d_state <= r6;
 163             when r6 =>
 164                d_state <= r7;
 165                dis_busy <= data_dis(7);
 166                E_dis <= '0';
 167             when r7 =>
 168                if dis_busy = '0' then -- uvidime noyna naopak
 169                   d_state <= idle;
 170                   interrupt_out <= '1';
 171                else
 172                   d_state <= r1;
 173                end if;
 174          end case;
 175       end if;
 176    end if;
 177  end process state_machyne_display;
 178  
 179  end Arch_Display_base;
 180  
 181  
Zobrazeno: 679454x Naposledy: 25.6.2022 21:05:21