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fpga /
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keyboard /
keyboard_ctrl_high.vhd
1 -- keyboard_ctrl.vhd : Keyboard controller
2 -- Copyright (C) 2006 Brno University of Technology,
3 -- Faculty of Information Technology
4 -- Author(s): Tomas Martinek <martinto AT fit.vutbr.cz>
5 --
6 -- LICENSE TERMS
7 --
8 -- Redistribution and use in source and binary forms, with or without
9 -- modification, are permitted provided that the following conditions
10 -- are met:
11 -- 1. Redistributions of source code must retain the above copyright
12 -- notice, this list of conditions and the following disclaimer.
13 -- 2. Redistributions in binary form must reproduce the above copyright
14 -- notice, this list of conditions and the following disclaimer in
15 -- the documentation and/or other materials provided with the
16 -- distribution.
17 -- 3. All advertising materials mentioning features or use of this software
18 -- or firmware must display the following acknowledgement:
19 --
20 -- This product includes software developed by the University of
21 -- Technology, Faculty of Information Technology, Brno and its
22 -- contributors.
23 --
24 -- 4. Neither the name of the Company nor the names of its contributors
25 -- may be used to endorse or promote products derived from this
26 -- software without specific prior written permission.
27 --
28 -- This software or firmware is provided ``as is'', and any express or implied
29 -- warranties, including, but not limited to, the implied warranties of
30 -- merchantability and fitness for a particular purpose are disclaimed.
31 -- In no event shall the company or contributors be liable for any
32 -- direct, indirect, incidental, special, exemplary, or consequential
33 -- damages (including, but not limited to, procurement of substitute
34 -- goods or services; loss of use, data, or profits; or business
35 -- interruption) however caused and on any theory of liability, whether
36 -- in contract, strict liability, or tort (including negligence or
37 -- otherwise) arising in any way out of the use of this software, even
38 -- if advised of the possibility of such damage.
39 --
40 -- $Id$
41 --
42 --
43
44 library IEEE;
45 use IEEE.STD_LOGIC_1164.ALL;
46 use IEEE.STD_LOGIC_ARITH.ALL;
47 use IEEE.STD_LOGIC_UNSIGNED.ALL;
48
49 entity keyboard_controller_high is
50 generic(
51 READ_INTERVAL : integer := (2**14)-1
52 );
53 port(
54 -- Hodiny a Reset
55 CLK : in std_logic;
56 RST : in std_logic;
57
58 -- Stisknute klavesy
59 DATA_OUT : out std_logic_vector(15 downto 0);
60
61 -- Signaly klavesnice
62 KB_KIN : out std_logic_vector(3 downto 0);
63 KB_KOUT : in std_logic_vector(3 downto 0)
64 );
65 end keyboard_controller_high;
66
67 architecture behavioral of keyboard_controller_high is
68
69 signal key_data_out : std_logic_vector(15 downto 0);
70 signal key_data_vld : std_logic;
71
72 begin
73
74 -- keyboard controller instantion
75 key_ctrl_u : entity work.keyboard_controller
76 generic map(
77 READ_INTERVAL => READ_INTERVAL
78 )
79 port map(
80 CLK => CLK,
81 RST => RST,
82
83 -- Stisknute klavesy
84 DATA_OUT => key_data_out,
85 DATA_VLD => key_data_vld,
86
87 -- Signaly klavesnice
88 KB_KIN => KB_KIN,
89 KB_KOUT => KB_KOUT
90 );
91
92 DATA_OUT(0) <= key_data_vld and key_data_out(7);
93 DATA_OUT(1) <= key_data_vld and key_data_out(0);
94 DATA_OUT(2) <= key_data_vld and key_data_out(4);
95 DATA_OUT(3) <= key_data_vld and key_data_out(8);
96 DATA_OUT(4) <= key_data_vld and key_data_out(1);
97 DATA_OUT(5) <= key_data_vld and key_data_out(5);
98 DATA_OUT(6) <= key_data_vld and key_data_out(9);
99 DATA_OUT(7) <= key_data_vld and key_data_out(2);
100 DATA_OUT(8) <= key_data_vld and key_data_out(6);
101 DATA_OUT(9) <= key_data_vld and key_data_out(10);
102 DATA_OUT(10) <= key_data_vld and key_data_out(12);
103 DATA_OUT(11) <= key_data_vld and key_data_out(13);
104 DATA_OUT(12) <= key_data_vld and key_data_out(14);
105 DATA_OUT(13) <= key_data_vld and key_data_out(15);
106 DATA_OUT(14) <= key_data_vld and key_data_out(3);
107 DATA_OUT(15) <= key_data_vld and key_data_out(11);
108
109 end behavioral;
110
111