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interrupt.vhd

   1  -- interrupt.vhd:
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Jan Markovic   xmarko04@stud.fit.vutbr.cz
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  
  45  library IEEE;
  46  use IEEE.std_logic_1164.ALL;
  47  use IEEE.std_logic_ARITH.ALL;
  48  use IEEE.std_logic_UNSIGNED.ALL;
  49  
  50  
  51  -- SYNTH-ISE-8.2: slices=9, slicesFF=16, 4luts=11
  52  entity interrupt_controller is
  53     generic (
  54        WIDTH : integer := 8 -- pocet vstupu preruseni
  55     );
  56     port (
  57        CLK    : in std_logic;
  58        RST    : in std_logic;
  59  
  60        -- preruseni zarizeni
  61        IRQ_IN  : in std_logic_vector(WIDTH-1 downto 0);
  62        IRQ_OUT : out std_logic;
  63  
  64        -- vektor preruseni
  65        DATA_OUT : out std_logic_vector(WIDTH-1 downto 0);
  66        READ_EN  : in std_logic;
  67  
  68        -- maska preruseni
  69        DATA_IN  : in std_logic_vector(WIDTH-1 downto 0);
  70        WRITE_EN : in std_logic
  71     );
  72  end interrupt_controller;
  73  
  74  architecture arch_interrupt of interrupt_controller is
  75  
  76     signal irqmask_reg   : std_logic_vector(WIDTH-1 downto 0);
  77     signal irqvector_reg : std_logic_vector(WIDTH-1 downto 0);
  78  
  79  begin
  80     -- IRQ vector
  81     DATA_OUT <= irqvector_reg;
  82  
  83     -- IRQ request output
  84     request:process(irqvector_reg)
  85     variable irqset : std_logic;
  86     begin
  87        irqset := '0';
  88        for i in 0 to (WIDTH-1) loop
  89           irqset := irqset or irqvector_reg(i);
  90        end loop;
  91        IRQ_OUT <= irqset;
  92     end process;
  93  
  94     -- Interrupt mask register
  95     mask: process(CLK, RST)
  96     begin
  97        if (RST = '1') then
  98           -- all interrupts are disabled default
  99           irqmask_reg  <= (others => '0');
 100        elsif (CLK'event) and (CLK = '1') then
 101           if (WRITE_EN = '1') then
 102              irqmask_reg <= DATA_IN;
 103           end if;
 104        end if;
 105     end process mask;
 106  
 107     --Interrupt vector register
 108     interrupt: process(CLK, RST)
 109     begin
 110        if (RST = '1') then
 111           irqvector_reg <= (others => '0');
 112        elsif (CLK'event) and (CLK = '1') then
 113           for i in 0 to WIDTH-1 loop
 114              if (READ_EN='1') then
 115                 -- IRQ served
 116                 irqvector_reg(i) <= '0';
 117              else
 118                 -- IRQ request
 119                 irqvector_reg(i) <= irqmask_reg(i) and (irqvector_reg(i) or IRQ_IN(i));
 120              end if;
 121           end loop;
 122        end if;
 123     end process interrupt;
 124  
 125  end arch_interrupt;
 126  
 127  
Zobrazeno: 679756x Naposledy: 28.6.2022 20:09:22