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Aktuální adresář: FITkit / trunk / fpga / ctrls / ide /

ide_port.vhd

   1  -- ide_port.vhd : IDE Port
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Stanislav Sigmund <xsigmu02 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  
  49  entity IDE_port is
  50     port (
  51        IDE : inout std_logic_vector(25 downto 0) := (others => 'Z');
  52        X   : inout std_logic_vector(45 downto 0) := (others => 'Z')
  53     );
  54  end IDE_port;
  55  
  56  architecture basic of IDE_port is
  57  begin
  58  idec: for i in 0 to 7 generate
  59   X(16-2*i) <= IDE(i);
  60   X(3+2*i) <= IDE(i+8);
  61  end generate;
  62  X(0) <= IDE(16); -- RESET
  63  X(22) <= IDE(17); -- IOW
  64  X(24) <= IDE(18); -- IOR
  65  
  66  X(37) <= IDE(23);X(36) <= IDE(22);
  67  X(35) <= IDE(21);X(32) <= IDE(20);
  68  X(34) <= IDE(19); -- CS1 CS0 DA2 DA1 DA0
  69  
  70  X(20) <= IDE(24);X(28) <= IDE(25); -- DMARQ DMAACK
  71  
  72  X(1) <= '0';X(18) <= '0';X(21) <= '0';X(23) <= '0';
  73  X(25) <= '0';X(29) <= '0';X(39) <= '0';
  74  
  75  -- nezapojene vyvody
  76  X(30) <= 'Z'; -- INTQ
  77  -- DASP- DIAG- IOCS16- CSEL
  78  X(38) <= 'Z';X(33) <= 'Z';X(31) <= 'Z';X(27) <= 'Z';
  79  -- IORDY keypin_20, nic nic
  80  X(26) <= 'Z';X(19) <= 'Z';X(40) <= 'Z';X(41) <= 'Z';
  81  -- nic nic nic nic
  82  X(42) <= 'Z';X(43) <= 'Z';X(44) <= 'Z';X(45) <= 'Z';
  83  end basic;
  84  
  85  architecture small of IDE_port is
  86  begin
  87  idec: for i in 0 to 7 generate
  88   X(14-2*i) <= IDE(i);
  89   X(1+2*i) <= IDE(i+8);
  90  end generate;
  91  X(16) <= IDE(16); -- RESET
  92  X(20) <= IDE(17); -- IOW
  93  X(22) <= IDE(18); -- IOR
  94  
  95  X(17) <= IDE(23);X(19) <= IDE(22);
  96  X(21) <= IDE(21);X(24) <= IDE(20);
  97  X(23) <= IDE(19); -- CS1 CS0 DA2 DA1 DA0
  98  
  99  IDE(24) <= X(18);X(26) <= IDE(25); -- DMARQ DMAACK
 100  
 101  -- nezapojene vyvody
 102  X(25) <= 'Z'; -- volne misto
 103  inz: for i in 27 to 45 generate
 104   X(i) <=  'Z';
 105  end generate;
 106  end small;
 107  
 108  architecture rotate of IDE_port is
 109  begin
 110  idec: for i in 0 to 7 generate
 111   X(23+2*i) <= IDE(i);
 112   X(36-2*i) <= IDE(i+8);
 113  end generate;
 114  X(39) <= IDE(16); -- RESET
 115  X(17) <= IDE(17); -- IOW
 116  X(15) <= IDE(18); -- IOR
 117  
 118  X(2) <= IDE(23);X(3) <= IDE(22);
 119  X(4) <= IDE(21);X(7) <= IDE(20);
 120  X(5) <= IDE(19); -- CS1 CS0 DA2 DA1 DA0
 121  
 122  X(19) <= IDE(24);X(11) <= IDE(25); -- DMARQ DMAACK
 123  
 124  X(38) <= '0';X(21) <= '0';X(18) <= '0';X(16) <= '0';
 125  X(14) <= '0';X(10) <= '0';-- X(0) <= '0';
 126  
 127  -- nezapojene vyvody
 128  X(9) <= 'Z'; -- INTQ
 129  -- DASP- DIAG- IOCS16- CSEL
 130  X(1) <= 'Z';X(6) <= 'Z';X(8) <= 'Z';X(12) <= 'Z';
 131  -- IORDY keypin_20, nic nic
 132  X(13) <= 'Z';X(20) <= 'Z';X(40) <= 'Z';X(41) <= 'Z';
 133  -- nic nic nic nic
 134  X(42) <= 'Z';X(43) <= 'Z';X(44) <= 'Z';X(45) <= 'Z';
 135  end rotate;
 136  
Zobrazeno: 679742x Naposledy: 28.6.2022 19:55:24