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ide_dma_ctrl.vhd

   1  -- ide_ctrl.vhd : IDE Controler
   2  -- Copyright (C) 2009 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Stanislav Sigmund <xsigmu02 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library ieee;
  45  use ieee.std_logic_1164.all;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  
  49  entity IDE_ctrl is
  50        generic (
  51           CLK_PERIOD  : integer := 20
  52        );
  53     port (
  54        -- Reset a synchronizace
  55        IDE     : inout std_logic_vector(25 downto 0) := (others => 'Z');
  56        CLK     : in std_logic; -- Hodiny radice (min. 4x vetsi, nez hodiny SPI)
  57        RST			:	in std_logic; -- RESET radice
  58        INTRQ		:	out std_logic;	-- Zadost o preruseni
  59  
  60        -- Interni rozhrani
  61        DI      : out std_logic;   -- Serial data out (MOSI)
  62        DI_REQ  : in std_logic;   -- DI request
  63        DO      : in std_logic;   -- Serial data in (MISO)
  64        DO_VLD  : in std_logic;   -- DO valid
  65        CS      : in std_logic    -- internal SPI active
  66     );
  67  end IDE_ctrl;
  68  
  69  architecture basic of IDE_ctrl is
  70  -- system casovani, zatim se pocita s PIO 0
  71  -- ior/iow ma byt nahozen az za 70 ns po platne adrese
  72  constant IORW_VALID : integer := 70 / CLK_PERIOD + 1; -- 4
  73  -- ior/iow ma drzet nejmene 290 ns (pro 8-bitovy rezim...)
  74  constant IORW_HOLD : integer := 290 / CLK_PERIOD; -- 14
  75  -- po shozeni iow maji byt data pritomna jeste min. 30 ns
  76  constant IOW_HOLD : integer := 30 / CLK_PERIOD + 1; -- 2
  77  -- po shozeni ior jsou data pritomna jeste 5ns - shodime ior pozdeji
  78  constant IOR_HOLD : integer := 5 / CLK_PERIOD + 1; -- 1
  79  
  80  constant IO_DELAY : integer := (IORW_HOLD + IORW_VALID + IOW_HOLD + 2);
  81  subtype tcntr is integer range 0 to (IORW_HOLD + 1);
  82  signal  delcntr : tcntr := 0; -- pocitadlo casovani
  83  signal  delcntr_rst : std_logic := '1'; -- povoleni pocitadla
  84      -- datove vodice d15 - d0:
  85  type    RWstate is (SIdle,SRAVld,SWAVld,SIowHold,SIorHold,SWHold,SRHold);
  86  signal  pstate    : RWstate := SIdle; -- actual state
  87  signal  nstate    : RWstate := SIdle; -- next state
  88  signal  cmp_avld : std_logic;
  89  signal  cmp_rwhold : std_logic;
  90  signal  cmp_rhold : std_logic;
  91  signal  cmp_whold : std_logic;
  92  -- signal  cmp_state_ch : std_logic;
  93  signal  state_ch : std_logic;
  94  
  95  
  96  --signal  data_out_mux : std_logic_vector(15 downto 0);
  97  signal  data    : std_logic_vector(15 downto 0) := (others => 'Z');
  98  signal  data_in  : std_logic_vector(16 downto 0);
  99  signal  data_in_valid : std_logic := '0';
 100  signal  data_out_buff : std_logic_vector(15 downto 0);
 101  signal  data_out : std_logic_vector(16 downto 0);
 102  signal  data_out_ready   : std_logic := '0';
 103  signal  DmaRQ   : std_logic;
 104  signal  DmaACK   : std_logic := '1';
 105  signal  iow     : std_logic := '1'; -- zapis na disk
 106  signal  ior     : std_logic := '1'; -- cteni z disku
 107  signal  read_data     : std_logic; -- chceme cist data
 108  signal  write_data    : std_logic; -- chceme zapsat data
 109  signal  ctrl_out : std_logic_vector(7 downto 0) := (others => '0');
 110  signal  ctrl_in : std_logic_vector(7 downto 0) := (others => '0');
 111  signal  ctrl_adc_out : std_logic_vector(7 downto 0) := (others => 'Z');
 112  signal  ctrl_write    : std_logic; -- chceme zapsat ridici bity
 113     -- adresace registru v disku, vyvody CS1, CS0, DA2, DA1, DA0
 114  signal  reg_addr: std_logic_vector(4 downto 0);
 115  signal  buff_addr: std_logic_vector(4 downto 0);
 116  signal  reg_adc_addr: std_logic_vector(4 downto 0);
 117  signal  reg_addr_ready : std_logic := '0';
 118  signal  Ctrl_Reg  : std_logic_vector(1 downto 0) := (others => '0');
 119  
 120  constant DEL_DMA_RW0 : integer := 240 / CLK_PERIOD; -- 12
 121  constant DEL_DMA_HOLD0 : integer := 280 / CLK_PERIOD; -- 14
 122  constant DEL_DMA_WAIT0 : integer := 480 / CLK_PERIOD; -- 24
 123  constant DEL_DMA_RW1 : integer := 80 / CLK_PERIOD; -- 4
 124  constant DEL_DMA_HOLD1 : integer := (100+CLK_PERIOD-1) / CLK_PERIOD; -- 5
 125  constant DEL_DMA_WAIT1 : integer := (150+CLK_PERIOD-1) / CLK_PERIOD; -- 8
 126  
 127  
 128  signal  BSDOut  : std_logic_vector(7 downto 0);
 129  signal  BSDIn  : std_logic_vector(7 downto 0);
 130  signal  BSAdr  : std_logic_vector(10 downto 0);
 131  signal  BSWe : std_logic := '0';
 132  signal  BDAdr  : std_logic_vector(9 downto 0) := (others => '0');
 133  signal  BDWe : std_logic := '0';
 134  signal  BDOutEn : std_logic := '0';
 135  signal  BDOut  : std_logic_vector(15 downto 0);
 136  
 137  constant SPD_VALID : integer := (70+CLK_PERIOD-1) / CLK_PERIOD; -- 4
 138  constant SPD_HOLD : integer := 360 / CLK_PERIOD; -- 18
 139  constant SPD_WAIT : integer := (390+CLK_PERIOD-1) / CLK_PERIOD; -- 20
 140  
 141  signal  spd_addr_en : std_logic := '0';
 142  signal  spd_out  : std_logic_vector(7 downto 0);
 143  signal  spd_addr  : std_logic_vector(4 downto 0);
 144  signal  spd_addr_buff  : std_logic_vector(4 downto 0);
 145  signal  spd_out_buff  : std_logic_vector(7 downto 0);
 146  signal  write_spd : std_logic := '0';
 147  signal  spd_en : std_logic := '0';
 148  signal  spd_iow : std_logic := '1';
 149  signal  SpdCnt : std_logic_vector(5 downto 0) := (others => '0');
 150  type    Spdstate is (SIdle,SVal,SHold,SWait);
 151  signal  pSstate    : Spdstate := SIdle; -- actual state
 152  signal  nSstate    : Spdstate := SIdle; -- next state
 153  signal  spdcmpval : std_logic := '0';
 154  signal  spdcmphold : std_logic := '0';
 155  signal  spdcmpwait : std_logic := '0';
 156  
 157  signal  DmaRun : std_logic := '0';
 158  signal  NDmaRun : std_logic := '1';
 159  signal  DmaRst : std_logic := '1';
 160  signal  DmaCtrlW  : std_logic := '0';
 161  signal  DmaBlock  : std_logic_vector(1 downto 0) := (others => '0');
 162  signal  DmaIRW : std_logic := '0';
 163  signal  DMA_Cnt_Rst : std_logic := '1';
 164  signal  DmaInc : std_logic := '0';
 165  signal  cmpDmaHold : std_logic := '0';
 166  signal  cmpDmaWait : std_logic := '0';
 167  signal  cmpDmaRW : std_logic := '0';
 168  signal  DmaEnd : std_logic := '0';
 169  signal  spd_res : std_logic := '0';
 170  signal  DmaCnt : std_logic_vector(5 downto 0) := (others => '0');
 171  signal  DmaSpd : std_logic := '0';
 172  signal  DmaDir : std_logic := '0';
 173  signal  NDmaDir   : std_logic := '1';
 174  type    DMAstate is (SIdle,SRun,SWR,SHold,SWait);
 175  signal  pDstate    : DMAstate := SIdle; -- actual state
 176  signal  nDstate    : DMAstate := SIdle; -- next state
 177  signal  BDOutWr : std_logic := '0';
 178  
 179     component SPI_adc
 180        generic (
 181           ADDR_WIDTH : integer;
 182           DATA_WIDTH : integer;
 183           ADDR_OUT_WIDTH : integer;
 184           BASE_ADDR  : integer;
 185           DELAY  : integer
 186        );
 187        port (
 188           CLK      : in  std_logic;
 189  
 190           CS       : in  std_logic;
 191           DO       : in  std_logic;
 192           DO_VLD   : in  std_logic;
 193           DI       : out std_logic;
 194           DI_REQ   : in  std_logic;
 195  
 196           ADDR     : out  std_logic_vector(ADDR_OUT_WIDTH-1 downto 0);
 197           DATA_OUT : out  std_logic_vector(DATA_WIDTH-1 downto 0);
 198           DATA_IN  : in   std_logic_vector(DATA_WIDTH-1 downto 0);
 199  
 200           WRITE_EN : out  std_logic;
 201           READ_EN  : out  std_logic
 202        );
 203     end component;
 204  
 205     for SPI_adc_data: SPI_adc use entity work.SPI_adc(autoincrement);
 206     for SPI_adc_spd: SPI_adc use entity work.SPI_adc(autoincrement);
 207  
 208     component RAMB16_S9_S18
 209     port (
 210        DIA   : in  std_logic_vector(7 downto 0);   -- DATA IN
 211        DIPA  : in  std_logic_vector(0 downto 0);    -- DATA IN PARITY
 212        ADDRA : in  std_logic_vector(10 downto 0);    -- ADDRESS
 213        ENA   : in  std_logic;                       -- ENABLE
 214        WEA   : in  std_logic;                       -- WRITE ENABLE
 215        SSRA  : in  std_logic;                       -- SET/RESET
 216        CLKA  : in  std_logic;                       -- CLK
 217        DOA   : out std_logic_vector(7 downto 0);   -- DATA OUT
 218        DOPA  : out std_logic_vector(0 downto 0);     -- DATA OUT PARITY
 219  
 220        DIB   : in  std_logic_vector(15 downto 0);   -- DATA IN
 221        DIPB  : in  std_logic_vector(1 downto 0);    -- DATA IN PARITY
 222        ADDRB : in  std_logic_vector(9 downto 0);    -- ADDRESS
 223        ENB   : in  std_logic;                       -- ENABLE
 224        WEB   : in  std_logic;                       -- WRITE ENABLE
 225        SSRB  : in  std_logic;                       -- SET/RESET
 226        CLKB  : in  std_logic;                       -- CLK
 227        DOB   : out std_logic_vector(15 downto 0);   -- DATA OUT
 228        DOPB  : out std_logic_vector(1 downto 0)    -- DATA OUT PARITY
 229     );
 230     end component;
 231  
 232  begin
 233  -- 0-15 data
 234  -- 16 RESET
 235  -- 17 IOW
 236  -- 18 IOR
 237  -- 19-23 DA0 DA1 DA2 CS0 CS1
 238  -- 24 DMARQ
 239  -- 25 DMAACK
 240  -- datove vodice
 241  idec: for i in 0 to 15 generate
 242   IDE(i) <= data(i);
 243  end generate;
 244  
 245  -- adresni vodice
 246  iaddr: for i in 0 to 4 generate
 247   IDE(19+i) <= reg_addr(i);
 248  end generate;
 249  
 250  DmaRQ <= IDE(24);IDE(25) <= DmaACK;
 251  BDOutWr <= '1' when (BDOutEn = '1' AND DmaDir = '1') else '0';
 252  
 253  data <= data_out_buff when data_out_ready='1' else
 254  				("00000000" & spd_out_buff) when spd_en='1' else
 255        	BDOut when BDOutWr='1' else
 256  				(others => 'Z');
 257  
 258  --data_out_mux <= BDOut when (BDOutWr = '1') else data_out_buff;
 259  --data <= data_out_mux when (data_out_ready = '1' OR BDOutWr = '1') else (others => 'Z');
 260  
 261  IDE(16) <= ctrl_out(0); -- RESET-
 262  ctrl_in <= DmaRun & DmaRQ & DmaSpd & DmaDir & "00" & DmaBlock(1 downto 0) when (Ctrl_Reg = "01") else
 263  DmaACK & DmaRQ & DmaIRW & reg_addr(4 downto 0);
 264  
 265  cmp_avld <= '1' when (delcntr = IORW_VALID) else '0';
 266  cmp_rwhold <= '1' when (delcntr = IORW_HOLD) else '0';
 267  cmp_rhold <= '1' when (delcntr = IOR_HOLD) else '0';
 268  cmp_whold <= '1' when (delcntr = IOW_HOLD) else '0';
 269  -- cmp_state_ch <= '0' when (pstate = nstate) else '1';
 270  
 271  reg_addr <= buff_addr when (reg_addr_ready = '1') else
 272    spd_addr_buff when (spd_addr_en = '1') else "11000";
 273  
 274  NDmaDir <= '1' when (DmaDir = '0') else '0';
 275  IDE(17) <= (iow AND spd_iow) when (DmaIRW='0') else NDmaDir;
 276  IDE(18) <= ior when (DmaIRW='0') else DmaDir;
 277  
 278     SPI_adc_cmd: SPI_adc
 279        generic map(
 280           ADDR_WIDTH => 15,
 281           DATA_WIDTH => 17,
 282           ADDR_OUT_WIDTH => 5,
 283           BASE_ADDR  => 16#0180#,
 284           DELAY  => IO_DELAY
 285        )
 286        port map(
 287           CLK      => CLK,
 288  
 289           CS       => CS,
 290           DO       => DO,
 291           DO_VLD   => DO_VLD,
 292           DI       => DI,
 293           DI_REQ   => DI_REQ,
 294  
 295           ADDR     => reg_adc_addr,
 296           DATA_IN  => data_in,
 297           READ_EN  => read_data,
 298  
 299           DATA_OUT => data_out,
 300           WRITE_EN => write_data
 301        );
 302  
 303     SPI_adc_spd: SPI_adc
 304        generic map(
 305           ADDR_WIDTH => 16,
 306           DATA_WIDTH => 8,
 307           ADDR_OUT_WIDTH => 5,
 308           BASE_ADDR  => 16#0000#,
 309           DELAY  => 0
 310        )
 311        port map(
 312           CLK      => CLK,
 313  
 314           CS       => CS,
 315           DO       => DO,
 316           DO_VLD   => DO_VLD,
 317           DI       => DI,
 318           DI_REQ   => DI_REQ,
 319  
 320           ADDR     => spd_addr,
 321           DATA_IN  => "00000000",
 322           READ_EN  => open,
 323  
 324           DATA_OUT => spd_out,
 325           WRITE_EN => write_spd
 326        );
 327  
 328     SPI_adc_ctrl: SPI_adc
 329        generic map(
 330           ADDR_WIDTH => 8,
 331           DATA_WIDTH => 8,
 332           ADDR_OUT_WIDTH => 2,
 333           BASE_ADDR  => 16#04#,
 334           DELAY => 1
 335        )
 336        port map(
 337           CLK      => CLK,
 338  
 339           CS       => CS,
 340           DO       => DO,
 341           DO_VLD   => DO_VLD,
 342           DI       => DI,
 343           DI_REQ   => DI_REQ,
 344  
 345           ADDR     => Ctrl_Reg,
 346           DATA_IN  => ctrl_in,
 347           READ_EN  => open,
 348  
 349           DATA_OUT => ctrl_adc_out,
 350           WRITE_EN => ctrl_write
 351        );
 352  
 353     SPI_adc_data: SPI_adc
 354        generic map(
 355           ADDR_WIDTH => 16,
 356           DATA_WIDTH => 8,
 357           ADDR_OUT_WIDTH => 11,
 358           BASE_ADDR  => 16#0800#,
 359           DELAY => 1
 360        )
 361        port map(
 362           CLK      => CLK,
 363  
 364           CS       => CS,
 365           DO       => DO,
 366           DO_VLD   => DO_VLD,
 367           DI       => DI,
 368           DI_REQ   => DI_REQ,
 369  
 370           ADDR     => BSAdr,
 371           DATA_IN  => BSDIn,
 372           READ_EN  => open,
 373  
 374           DATA_OUT => BSDOut,
 375           WRITE_EN => BSWe
 376        );
 377  
 378     BUF: RAMB16_S9_S18
 379     port map(
 380        DIA   => BSDOut,
 381        DIPA  => "0",
 382        ADDRA => BSAdr,
 383        ENA   => '1',
 384        WEA   => BSWe,
 385        SSRA  => '0',
 386        CLKA  => CLK,
 387        DOA   => BSDIn,
 388        DOPA  => open,
 389  
 390        DIB   => data,
 391        DIPB  => "00",
 392        ADDRB => BDAdr,
 393        ENB   => '1',
 394        WEB   => BDWe,
 395        SSRB  => '0',
 396        CLKB  => CLK,
 397        DOB   => BDOut,
 398        DOPB  => open
 399     );
 400  
 401  spdcmpval <= '1' when (SpdCnt = SPD_VALID) else '0';
 402  spdcmphold <= '1' when (SpdCnt = SPD_HOLD) else '0';
 403  spdcmpwait <= '1' when (SpdCnt = SPD_WAIT) else '0';
 404  
 405     spd_addr_store: process(CLK)
 406     begin
 407        if CLK'event and CLK = '1' then
 408        	if write_spd = '1' then
 409        		spd_addr_buff <= spd_addr;
 410        		spd_out_buff <= spd_out;
 411  				end if;
 412        end if;
 413     end process;
 414  
 415     spd_cnt: process(CLK,spd_res)
 416     begin
 417     		if spd_res = '1' then
 418     			SpdCnt <= (others => '0');
 419     		elsif CLK'event and CLK = '1' then
 420       		SpdCnt <= SpdCnt + 1;
 421        end if;
 422     end process;
 423  
 424     spd_tick: process(CLK,RST)
 425     begin
 426    		if RST = '1' then
 427    			pSstate <= SIdle;
 428        elsif CLK'event and CLK = '1' then
 429  				pSstate <= nSstate;
 430        end if;
 431     end process;
 432  
 433     spd_FSA: process(pSstate,spdcmpval,spdcmphold,spdcmpwait,write_spd)
 434     begin
 435        case pSstate is
 436          when SIdle =>
 437  		   		nSstate <= SIdle;
 438          	if write_spd = '1' then
 439  	       		nSstate <= SVal;
 440  	       	end if;
 441          when SVal =>
 442         		nSstate <= SVal;
 443          	if (spdcmpval = '1') then
 444          		nSstate <= SHold;
 445          	end if;
 446          when SHold =>
 447        		nSstate <= SHold;
 448          	if (spdcmphold = '1') then
 449          		nSstate <= SWait;
 450          	end if;
 451          when SWait =>
 452         		nSstate <= SWait;
 453          	if (spdcmpwait = '1') then
 454          		nSstate <= SIdle;
 455          	end if;
 456       end case;
 457     end process;
 458  
 459     spd_logic: process(pSstate)
 460     begin
 461     		spd_addr_en <= '0';
 462     		spd_en <= '0';
 463     		spd_iow <= '1';
 464     		spd_res <= '0';
 465        case pSstate is
 466          when SIdle =>
 467  		   		spd_res <= '1';
 468          when SVal =>
 469     				spd_addr_en <= '1';
 470          when SHold =>
 471     				spd_addr_en <= '1';
 472     				spd_iow <= '0';
 473     				spd_en <= '1';
 474          when SWait =>
 475     				spd_en <= '1';
 476     				spd_addr_en <= '1';
 477       end case;
 478     end process;
 479  
 480  -- ******** normal *******
 481  
 482     data_store: process(CLK)
 483     begin
 484        if CLK'event and CLK = '1' then
 485        	if write_data = '1' then
 486        		data_out_buff <= data_out(15 downto 0);
 487  				end if;
 488        end if;
 489     end process;
 490  
 491     data_in_store: process(CLK)
 492     begin
 493        if CLK'event and CLK = '1' then
 494        	if data_in_valid = '1' then
 495        		data_in <= '0' & data;
 496  				end if;
 497        end if;
 498     end process;
 499  
 500     addr_store: process(CLK)
 501     begin
 502        if CLK'event and CLK = '1' then
 503        	if (read_data = '1') or (write_data = '1') then
 504        		buff_addr <= reg_adc_addr;
 505  				end if;
 506        end if;
 507     end process;
 508  
 509     ctrl_set: process(CLK,RST)
 510     begin
 511    		if RST = '1' then
 512  			  ctrl_out <= (others => '0');
 513  			elsif CLK'event and CLK = '1' then
 514           if ctrl_write = '1' AND Ctrl_Reg = "00" then
 515           	ctrl_out <= ctrl_adc_out;
 516           end if;
 517        end if;
 518     end process;
 519  
 520     rw_tick: process(CLK,RST)
 521     begin
 522    		if RST = '1' then
 523    			pstate <= SIdle;
 524        elsif CLK'event and CLK = '1' then
 525  				pstate <= nstate;
 526        end if;
 527     end process;
 528  
 529     del_tick: process(CLK,delcntr_rst)
 530     begin
 531    		if delcntr_rst = '1' then
 532    			delcntr <= 0;
 533        elsif CLK'event and CLK = '1' then
 534        	if state_ch = '1' then
 535        		delcntr <= 0;
 536        	else
 537  					delcntr <= delcntr + 1;
 538  	      end if;
 539        end if;
 540     end process;
 541  
 542     rw_FSA: process(pstate,cmp_avld,cmp_rwhold,cmp_rhold,cmp_whold,read_data,write_data)
 543     begin
 544  	   	state_ch <= '0';
 545        case pstate is
 546          --RW Idle
 547          when SIdle =>
 548  		   		nstate <= SIdle;
 549          	if read_data = '1' then
 550  	       		nstate <= SRAVld;
 551  				   	state_ch <= '1';
 552  	       	elsif write_data = '1' then
 553  	       		nstate <= SWAVld;
 554  				   	state_ch <= '1';
 555  	       	end if;
 556          when SRAVld =>
 557         		nstate <= SRAVld;
 558          	if (cmp_avld = '1') then
 559          		nstate <= SIorHold;
 560  				   	state_ch <= '1';
 561          	end if;
 562          when SWAVld =>
 563         		nstate <= SWAVld;
 564          	if (cmp_avld = '1') then
 565          		nstate <= SIowHold;
 566  				   	state_ch <= '1';
 567          	end if;
 568          when SIorHold =>
 569         		nstate <= SIorHold;
 570          	if (cmp_rwhold = '1') then
 571          		nstate <= SRHold;
 572  				   	state_ch <= '1';
 573          	end if;
 574          when SIowHold =>
 575         		nstate <= SIowHold;
 576          	if (cmp_rwhold = '1') then
 577          		nstate <= SWHold;
 578  				   	state_ch <= '1';
 579          	end if;
 580          when SRHold =>
 581         		nstate <= SRHold;
 582          	if (cmp_rhold = '1') then
 583          		nstate <= SIdle;
 584  				   	state_ch <= '1';
 585          	end if;
 586          when SWHold =>
 587         		nstate <= SWHold;
 588          	if (cmp_whold = '1') then
 589          		nstate <= SIdle;
 590  				   	state_ch <= '1';
 591          	end if;
 592       end case;
 593     end process;
 594  
 595     rw_logic: process(pstate)
 596     begin
 597        data_out_ready <= '0';
 598        ior <= '1';
 599        iow <= '1';
 600        data_in_valid <= '0';
 601        reg_addr_ready <= '1';
 602        delcntr_rst <= '0';
 603        case pstate is
 604          --RW Idle
 605          when SIdle =>
 606  		      delcntr_rst <= '1';
 607  		      reg_addr_ready <= '0';
 608          when SRAVld =>
 609          when SWAVld =>
 610          when SIorHold =>
 611  		      ior <= '0';
 612  		      data_in_valid <= '1';
 613          when SIowHold =>
 614  		      iow <= '0';
 615            data_out_ready <= '1';
 616          when SRHold =>
 617          when SWHold =>
 618            data_out_ready <= '1';
 619       end case;
 620     end process;
 621  
 622  -- ******************* DMA Sekce ********************
 623  -- ctrl registr = R/W: DmaRun DmaRst DmaSpd DmaDir N/A N/A DmaBlock(2)
 624  -- DmaSpd = 0/1 -> Dma0/Dma1
 625  -- DmaDir = 0/1 -> R/W
 626  -- pri R je misto DmaRst DmaRQ
 627  
 628  DmaCtrlW <= '1' when ctrl_write = '1' AND Ctrl_Reg = "01" else '0';
 629  DmaRst <= ctrl_adc_out(6) OR RST when Ctrl_Reg = "01" else RST;
 630  NDmaRun <= '0' when (DmaRun = '1' AND DmaRQ = '1') else '1';
 631  DmaEnd <= '0' when (BDAdr(9 downto 8) = DmaBlock(1 downto 0)) else '1';
 632  cmpDmaRW <= '1' when (DmaCnt = DEL_DMA_RW0 AND DmaSpd = '0') OR
 633  	(DmaCnt = DEL_DMA_RW1 AND DmaSpd = '1') else '0';
 634  cmpDmaHold <= '1' when (DmaCnt = DEL_DMA_HOLD0 AND DmaSpd = '0') OR
 635  	(DmaCnt = DEL_DMA_HOLD1 AND DmaSpd = '1') else '0';
 636  cmpDmaWait <= '1' when (DmaCnt = DEL_DMA_WAIT0 AND DmaSpd = '0') OR
 637  	(DmaCnt = DEL_DMA_WAIT1 AND DmaSpd = '1') else '0';
 638  
 639     ctrl_dma_set: process(CLK,RST)
 640     begin
 641    		if RST = '1' then
 642  			  DmaRun <= '0';
 643  			  DmaSpd <= '0';
 644  			elsif CLK'event and CLK = '1' then
 645           if DmaCtrlW = '1' then
 646           	DmaBlock <= ctrl_adc_out(1 downto 0);
 647           	DmaRun <= ctrl_adc_out(7);
 648           	DmaSpd <= ctrl_adc_out(5);
 649           	DmaDir <= ctrl_adc_out(4);
 650           else
 651            if DmaEnd = '1' then DmaRun <= '0';
 652            end if;
 653           end if;
 654        end if;
 655     end process;
 656  
 657     Dma_Addr: process(CLK,DmaRst)
 658     begin
 659     		if DmaRst = '1' then
 660     			BDAdr(7 downto 0) <= (others => '0');
 661     		else
 662  	      if CLK'event and CLK = '1' then
 663  	        if DmaCtrlW = '1' then
 664  	          BDAdr(9 downto 8) <= ctrl_adc_out(1 downto 0);
 665  	        else
 666  		      	if DmaInc = '1' then
 667  		      		BDAdr <= BDAdr + 1;
 668  						end if;
 669  					end if;
 670  	      end if;
 671  	    end if;
 672     end process;
 673  
 674     DMA_tick: process(CLK,DmaRst)
 675     begin
 676    		if DmaRst = '1' then
 677    			pDstate <= SIdle;
 678        elsif CLK'event and CLK = '1' then
 679  				pDstate <= nDstate;
 680        end if;
 681     end process;
 682  
 683     DMA_cnt_tick: process(CLK,DMA_Cnt_Rst,DmaRst)
 684     begin
 685    		if DmaRst = '1' then
 686    			DmaCnt <= (others => '0');
 687        elsif CLK'event and CLK = '1' then
 688        	if DMA_Cnt_Rst = '1' then
 689        		DmaCnt <= (others => '0');
 690        	else
 691  					DmaCnt <= DmaCnt + 1;
 692  	      end if;
 693        end if;
 694     end process;
 695  
 696     DMA_FSA: process(pDstate,DmaRun,cmpDmaRW,cmpDmaHold,cmpDmaWait,DMARQ,DmaEnd,NDmaDir)
 697     begin
 698        BDWe <= '0';
 699        DmaInc <= '0';
 700        case pDstate is
 701          when SIdle =>
 702  		   		nDstate <= SIdle;
 703          	if (DmaRun = '1') AND (DmaEnd = '0') then
 704  	       		nDstate <= SRun;
 705  	       	end if;
 706          when SRun =>
 707  		   		nDstate <= SRun;
 708          	if (DmaRun = '1') AND (DmaRQ = '1') then
 709  	       		nDstate <= SWR;
 710  	       	end if;
 711          when SWR =>
 712         		nDstate <= SWR;
 713          	if (cmpDmaRW = '1') then
 714          		nDstate <= SHold;
 715          		BDWe <= NDmaDir;
 716          	end if;
 717          when SHold =>
 718         		nDstate <= SHold;
 719          	if (cmpDmaHold = '1') then
 720          		nDstate <= SWait;
 721          		DmaInc <= '1';
 722          	end if;
 723          when SWait =>
 724         		nDstate <= SWait;
 725         		if (DmaEnd = '1') then
 726          		nDstate <= SIdle;
 727          	else
 728  	        	if (cmpDmaWait = '1') then
 729  	        		nDstate <= SRun;
 730  	        	end if;
 731  	        end if;
 732       end case;
 733     end process;
 734  
 735     DMA_logic: process(pDstate,NDmaRun)
 736     begin
 737        BDOutEn <= '0';
 738        DmaIRW <= '0';
 739        DMA_Cnt_Rst <= '0';
 740        DmaACK <= '1';
 741        case pDstate is
 742          --RW Idle
 743          when SIdle =>
 744  		      DMA_Cnt_Rst <= '1';
 745          when SRun =>
 746        		DmaACK <= NDmaRun;
 747  		      DMA_Cnt_Rst <= '1';
 748          when SWR =>
 749            DmaIRW <= '1';
 750            BDOutEn <= '1';
 751        		DmaACK <= '0';
 752          when SHold =>
 753        		DmaACK <= '0';
 754            BDOutEn <= '1';
 755          when SWait =>
 756        		DmaACK <= '0';
 757       end case;
 758     end process;
 759  end basic;
 760