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top_level.vhd

   1  -- top_level.vhd: BRAM demo
   2  -- Copyright (C) 2006 Brno University of Technology,
   3  --                    Faculty of Information Technology
   4  -- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
   5  --
   6  -- LICENSE TERMS
   7  --
   8  -- Redistribution and use in source and binary forms, with or without
   9  -- modification, are permitted provided that the following conditions
  10  -- are met:
  11  -- 1. Redistributions of source code must retain the above copyright
  12  --    notice, this list of conditions and the following disclaimer.
  13  -- 2. Redistributions in binary form must reproduce the above copyright
  14  --    notice, this list of conditions and the following disclaimer in
  15  --    the documentation and/or other materials provided with the
  16  --    distribution.
  17  -- 3. All advertising materials mentioning features or use of this software
  18  --    or firmware must display the following acknowledgement:
  19  --
  20  --      This product includes software developed by the University of
  21  --      Technology, Faculty of Information Technology, Brno and its
  22  --      contributors.
  23  --
  24  -- 4. Neither the name of the Company nor the names of its contributors
  25  --    may be used to endorse or promote products derived from this
  26  --    software without specific prior written permission.
  27  --
  28  -- This software or firmware is provided ``as is'', and any express or implied
  29  -- warranties, including, but not limited to, the implied warranties of
  30  -- merchantability and fitness for a particular purpose are disclaimed.
  31  -- In no event shall the company or contributors be liable for any
  32  -- direct, indirect, incidental, special, exemplary, or consequential
  33  -- damages (including, but not limited to, procurement of substitute
  34  -- goods or services; loss of use, data, or profits; or business
  35  -- interruption) however caused and on any theory of liability, whether
  36  -- in contract, strict liability, or tort (including negligence or
  37  -- otherwise) arising in any way out of the use of this software, even
  38  -- if advised of the possibility of such damage.
  39  --
  40  -- $Id$
  41  --
  42  --
  43  
  44  library IEEE;
  45  use IEEE.std_logic_1164.ALL;
  46  use ieee.std_logic_arith.all;
  47  use ieee.std_logic_unsigned.all;
  48  
  49  architecture arch_beh of tlv_bare_ifc is
  50  
  51     signal bram_addr     : std_logic_vector(9 downto 0);
  52     signal bram_data_out : std_logic_vector(15 downto 0);
  53     signal bram_data_in  : std_logic_vector(15 downto 0);
  54     signal bram_we       : std_logic;
  55     signal bram_en       : std_logic;
  56  
  57     -- pouzite komponenty
  58     component SPI_adc
  59        generic (
  60           ADDR_WIDTH : integer;
  61           DATA_WIDTH : integer;
  62           ADDR_OUT_WIDTH : integer;
  63           BASE_ADDR  : integer
  64        );
  65        port (
  66           CLK      : in  std_logic;
  67  
  68           CS       : in  std_logic;
  69           DO       : in  std_logic;
  70           DO_VLD   : in  std_logic;
  71           DI       : out std_logic;
  72           DI_REQ   : in  std_logic;
  73  
  74           ADDR     : out std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
  75           DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
  76           DATA_IN  : in  std_logic_vector (DATA_WIDTH-1 downto 0);
  77  
  78           WRITE_EN : out std_logic;
  79           READ_EN  : out std_logic
  80        );
  81     end component;
  82  
  83     component RAMB16_S18
  84        port (
  85           DO   : out std_logic_vector(15 downto 0);
  86           DOP  : out std_logic_vector(1 downto 0);
  87           ADDR : in std_logic_vector(9 downto 0);
  88           CLK  : in std_ulogic;
  89           DI   : in std_logic_vector(15 downto 0);
  90           DIP  : in std_logic_vector(1 downto 0);
  91           EN   : in std_ulogic;
  92           SSR  : in std_ulogic;
  93           WE   : in std_ulogic
  94        );
  95     end component;
  96  
  97  begin
  98     -- SPI dekoder pro displej
  99     spidecd: SPI_adc
 100        generic map (
 101           ADDR_WIDTH => 16,      -- sirka adresy 16 bitu
 102           DATA_WIDTH => 16,      -- sirka dat 16 bitu
 103           ADDR_OUT_WIDTH => 10,  -- sirka adresy k adresaci BRAM 10 bitu
 104           BASE_ADDR  => 16#0000# -- adresovy prostor od 0x0000 - 0x03FF
 105        )
 106        port map (
 107           CLK      => CLK,
 108           CS       => SPI_CS,
 109  
 110           DO       => SPI_DO,
 111           DO_VLD   => SPI_DO_VLD,
 112           DI       => SPI_DI,
 113           DI_REQ   => SPI_DI_REQ,
 114  
 115           ADDR     => bram_addr,
 116           DATA_OUT => bram_data_in,
 117           DATA_IN  => bram_data_out,
 118           WRITE_EN => bram_we,
 119           READ_EN  => bram_en
 120        );
 121  
 122     -- Block RAM
 123     blkram: RAMB16_S18
 124        port map (
 125           CLK  => CLK,
 126           DO   => bram_data_out,
 127           DI   => bram_data_in,
 128           ADDR => bram_addr,
 129           EN   => '1',
 130           SSR  => '0',
 131           WE   => bram_we,
 132           DOP  => open,
 133           DIP  => "00"
 134        );
 135  
 136  end arch_beh;
 137  
Zobrazeno: 695381x Naposledy: 19.8.2022 13:30:09