00001 /******************************************************************************* 00002 fspi.c: second SPI interface 00003 Copyright (C) 2009 Brno University of Technology, 00004 Faculty of Information Technology 00005 Author(s): Karel Slany <slany AT fit.vutbr.cz> 00006 00007 LICENSE TERMS 00008 00009 Redistribution and use in source and binary forms, with or without 00010 modification, are permitted provided that the following conditions 00011 are met: 00012 1. Redistributions of source code must retain the above copyright 00013 notice, this list of conditions and the following disclaimer. 00014 2. Redistributions in binary form must reproduce the above copyright 00015 notice, this list of conditions and the following disclaimer in 00016 the documentation and/or other materials provided with the 00017 distribution. 00018 3. All advertising materials mentioning features or use of this software 00019 or firmware must display the following acknowledgement: 00020 00021 This product includes software developed by the University of 00022 Technology, Faculty of Information Technology, Brno and its 00023 contributors. 00024 00025 4. Neither the name of the Company nor the names of its contributors 00026 may be used to endorse or promote products derived from this 00027 software without specific prior written permission. 00028 00029 This software or firmware is provided ``as is'', and any express or implied 00030 warranties, including, but not limited to, the implied warranties of 00031 merchantability and fitness for a particular purpose are disclaimed. 00032 In no event shall the company or contributors be liable for any 00033 direct, indirect, incidental, special, exemplary, or consequential 00034 damages (including, but not limited to, procurement of substitute 00035 goods or services; loss of use, data, or profits; or business 00036 interruption) however caused and on any theory of liability, whether 00037 in contract, strict liability, or tort (including negligence or 00038 otherwise) arising in any way out of the use of this software, even 00039 if advised of the possibility of such damage. 00040 00041 $Id$ 00042 00043 00044 *******************************************************************************/ 00045 00046 #include "fspi.h" 00047 00051 void FSPI_Init(char smclkdiv) 00052 { 00053 #if defined MSP_16X 00054 while(1) {} //FITkit 1.x not supported 00055 00056 /* 00057 // set SPI to UART0 (FITkit 1.x) 00058 00059 U0CTL |= SWRST; /// reset SPI 00060 U0CTL = SWRST | CHAR | SYNC | MM; /// SPI mode, 8 bit, master mode 00061 U0TCTL = CKPL | SSEL_3 | STC; /// SMCLK clock (7MHz), idle polarity 1 00062 U0BR0 = 2; /// max speed (SMCLK/2) 00063 U0BR1 = 0; 00064 ME2 |= USPIE1; /// enable SPI 00065 00066 // I/O setup 00067 FSPI_PORT_DIR &= ~(FSPI_DI); // inputs 00068 FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK; // outputs 00069 FSPI_PORT_OUT |= FSPI_DO | FSPI_CLK; // set outputs to 1 00070 00071 FSPI_PORT_SEL |= FSPI_DI | FSPI_DO | FSPI_CLK; // connects pins to USART 00072 00073 U0CTL &= ~SWRST; // enable SPI (disable reset) 00074 */ 00075 #elif defined MSP_261X 00076 // set SPI to UCB0 (FITkit 2.x) 00077 00078 UCB0CTL1 = UCSWRST; 00079 00080 UCB0CTL0 = UCCKPH | UCMST | UCMSB | UCMODE_0 | UCSYNC; 00081 UCB0CTL1 |= UCSSEL_2; 00082 UCB0BR0 = smclkdiv; 00083 UCB0BR1 = 0; 00084 00085 // I/O setup 00086 FSPI_PORT_DIR &= ~(FSPI_DI); // inputs 00087 FSPI_PORT_DIR |= FSPI_DO | FSPI_CLK | FSPI_CS; // outputs 00088 FSPI_PORT_OUT &= ~FSPI_CLK; // set outputs to 0 00089 FSPI_PORT_OUT |= FSPI_DO | FSPI_CS; // set outputs to 1 00090 00091 FSPI_PORT_SEL |= SPI_DI | SPI_DO | SPI_CLK; // connects pins to UCB0 00092 00093 //UC1IFG = 0; 00094 UC0IE &= ~(UCB0TXIE | UCB0RXIE); 00095 00096 UCB0CTL1 &= ~UCSWRST; // disable UCB0 reset 00097 #else 00098 #error "Can't initialize SPI" 00099 #endif 00100 } 00101 00102 00106 void FSPI_Close(void) 00107 { 00108 #if defined MSP_16X 00109 /* 00110 // disable SPI 00111 ME2 &= ~USPIE1; // enable SPI 00112 U0CTL = SWRST; // disable (reset) SPI 00113 */ 00114 #elif defined MSP_261X 00115 UCB0CTL1 |= UCSWRST; 00116 #endif 00117 00118 // disable I/O 00119 FSPI_PORT_SEL &= ~(FSPI_DI | FSPI_DO | FSPI_CLK); // disconnect pins USART0 SPI 00120 FSPI_PORT_DIR &= ~(FSPI_DI | FSPI_DO | FSPI_CLK | FSPI_CS); // set all as inputs 00121 } 00122 00126 inline unsigned char FSPI_write_wait_read(unsigned char data) 00127 { 00128 FSPI_TX_BUF = data; 00129 while (FSPI_BUSY) {WDG_reset();} 00130 return FSPI_RX_BUF; 00131 } 00132 00136 inline void FSPI_write_wait(unsigned char data) 00137 { 00138 FSPI_TX_BUF = data; 00139 while (FSPI_BUSY) {WDG_reset();} 00140 }